[SI-LIST] Re: ESD structure for an inverter


Haritha,

A  simple inverter as a driver can also play the role of an ESD
device because the NMOS/PMOS can be a punchthrough device
at ESD stress.  However, the drain diffusion area would be larger
than an ordinary inverter that the cap. loading of the output pad
is larger.  You have to consult your foundry about the exact layout
rules for this frontend driver.  At the receiver side you do need a
dedicated one, with which the structure is a bit different than the
driver side.  In 0.35um technology the additional device may costs
you 1~2PF more capacitance and some silicon area, together with
a reverse-biased path from input to GND/VDD.

For more information I would recommend a book:

"ESD in Silicon Integrated Circuits" by Ajith Amerasekera,
Wiley, ISBN 0 471 95481 0

Good luck,
Raymond





"Haritha Chanda" <chandaharitha@xxxxxxxxx> on 05/02/2004 09:12:39

Please respond to chandaharitha@xxxxxxxxx

To:   si-list@xxxxxxxxxxxxx
cc:    (bcc: Raymond Leung/sdc)

Subject:  [SI-LIST] ESD structure for an inverter



Hi

I would like to know how the simple ESD structure would be for a
simple inverter acting as a driver and also as a receiver?

I am trying to understand how placing an ESD can affect the
performance parameters of the receiver and driver.So I am starting
off with simple inverter as driver and receiver.What performance
parameters do we need to look into?What are the typical sizes of
inverter as a driver and as a receiver in 0.35um technology?

If anyone has good source on ESD structures for simple inverter will
you please let me know.

Thank you.
Haritha



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