[SI-LIST] Re: ESD simulations
- From: Srivats Partha <vats123@xxxxxxxxx>
- To: starsilic@xxxxxxxxx, si-list@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 28 Nov 2006 12:35:28 -0800 (PST)
Hello ppl
I feel hspice wll not allow you to simulate the ESD compliance of a I/O pad.The
reason being HSPICE will not simulate a MOSFET beyond the saturation region.
Using HSPICE only the linear and saturation regions of a MOSFET can be
simulated. But to verify the ESD complaince MOSFET characteristics beyond
saturation in break down and snap back needs to be studied. The lateral PNP BJT
formed after the MOSFET breakdown needs to be studied. I am not sure if there
is a method to study this unless yu do the simulations with a MOSFET and a PNP
transistor connected. You may also have to model the current source which
depicts the Avalanche characteristics. Thats how we are looking to study the
ESD characteristics in our lab. I hope my explanation is on the right track.
Else you might have to use simulators which study MOSFET behavior in the high
current , voltage region. I wud very interested to know if there are other
methods to do this.
cheers
srivats
--
P.Srivatsan
Graduate Student
ECE Dept,North Carolina State University
http://www4.ncsu.edu/~spartha2/
--
I have no special talents. I am only passionately curious. AE
----- Original Message ----
From: Yafei Bi <yafei_bi@xxxxxxxxx>
To: starsilic@xxxxxxxxx; si-list@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Sent: Monday, November 27, 2006 1:01:49 PM
Subject: [SI-LIST] Re: ESD simulations
if you have the device model for the ESD protection devices/network, then y=
ou can build the test benches for ESD event(HBM, CBM etc.), and simulate ES=
D event/compliance in HSpice. That will give you some idea on whether the I=
/O design can meet the ESD requirement or not.=0A=0AIf you don't have ESD d=
evice model, then you have to use T-CAD to generate the I-V characteristic =
of the protection devices. Hopely you can do the same experiment on the dev=
ice and see the difference.=0A=0AEventually, ESD test on silicon is the fin=
al proof.=0A=0Abest,=0A=0AYafei=0A=0A----- Original Message ----=0AFrom: Ca=
nes Venatici <starsilic@xxxxxxxxx>=0ATo: si-list@xxxxxxxxxxxxx; si-list@fre=
elists.org=0ASent: Monday, November 27, 2006 2:50:26 AM=0ASubject: [SI-LIST=
] ESD simulations=0A=0AHi all,=0AIs it possible to do ESD simulation of I/O=
pad using H-spice. =0AShould we use process/device simulators like T-CAD (=
Synopsys) for=0Athis.=0AHow can we say the device fails due to ESD, by simu=
lation.=0AIn essence how can we say a particular i/o pad is ESD proof.=0AAn=
y help is strongly appreciated,=0ACanes=0A=0A=0A=0A=0A =0A_________________=
___________________________________________________________________=0ADo yo=
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