[SI-LIST] Re: ESD is a low frequency event -really??

Michael, I have several variations on the model that can be found in quite 
a bit of literature.  The primitive form of the nine element model is:
R1 1 11 = ESR_CELL * 4
R2 2 21 = ESR_CELL * 4
R3 3 31 = ESR_CELL * 4
R4 4 41 = ESR_CELL * 4
L1 11 100 = ESL_SHEET * 2
L2 21 100 = ESL_SHEET * 2
L3 31 100 = ESL_SHEET * 2
L4 41 100 = ESL_SHEET * 2
C1 100 5 = CCELL

Externally, node 5 connects to global node 0, and nodes 1-4 are the 
corners.  The required capacitance is just the parallel plate capacitance 
of the cell.  The required inductance of each inductor is twice the area 
inductance of the entire sheet, not the cell.  The value of the resistance 
at DC is twice the value of the cell area as a strip.  Depending on your 
version of SPICE, you may be able to easily include skin effect.  IS-SPICE 
does this nicely.

For a seventeen element model, there are four differential ports, and no 
external node 0 port:

R1 1 11 = ESR_CELL * 2
R2 2 21 = ESR_CELL * 2
R3 3 31 = ESR_CELL * 2
R4 4 41 = ESR_CELL * 2
R5 5 51 = ESR_CELL * 2
R6 6 61 = ESR_CELL * 2
R7 7 71 = ESR_CELL * 2
R8 8 81 = ESR_CELL * 2
L1 11 100 = ESL_SHEET
L2 21 100 = ESL_SHEET
L3 31 100 = ESL_SHEET
L4 41 100 = ESL_SHEET
L5 51 101 = ESL_SHEET
L6 61 101 = ESL_SHEET
L7 71 101 = ESL_SHEET
L8 81 101 = ESL_SHEET
C1 100 101 = CCELL

Regards,


Steve.
At 02:19 PM 3/23/2004 -0800, you wrote:
>Hi Steve,
>
>Could you post the bedspring model with estimated component valued?  I
>would like to see a little clearer what you are describing.
>
>Thanks,
>
>Michael
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of steve weir
>Sent: Wednesday, March 17, 2004 3:17 PM
>To: Chris Cheng
>Cc: 'si-list@xxxxxxxxxxxxx'
>Subject: [SI-LIST] Re: ESD is a low frequency event -really??
>
>Great!  The CY's as capacitors are just a convenience to me as they
>already
>had the R/L built in and it makes the network look like an AC line EMI
>filter.  The capacitance is irrelevant as long as it is big enough.
>
>Now an interesting thing that is going to come up is that if we take the
>
>voltage plane to be along the R1 / L1 line, then CY1n is going to have a
>
>large impedance.  So, if we build a bedspring model, I think we want to
>remove the connection from R1 to node 1.  We can then inject noise at
>node
>1 and see how the whole thing behaves, including the other voltage plane
>
>13, etc which is not covered in Doug's experiment.
>
>Regards,
>
>
>Steve.
>
>
>At 03:05 PM 3/17/2004 -0800, Chris Cheng wrote:
> >Got it, I always want to build models that can correlate with
>experimental
> >measurement rather than speculation.
> >I think we can see whether adding ZYx (it looks more like shunt
>impedance
> >than capacitance to me) is more effective than changing CX.
> >And the experiment suggest adding ZYx is a more effective way, well...
> >consider the trouble is already done to build the tightly connected
>chassis
> >ring at the peripheral.
> >
> >-----Original Message-----
> >From: steve weir [mailto:weirsp@xxxxxxxxxx]
> >Sent: Wednesday, March 17, 2004 2:39 PM
> >To: Chris Cheng; Chris Cheng
> >Cc: 'si-list@xxxxxxxxxxxxx'
> >Subject: RE: [SI-LIST] Re: ESD is a low frequency event -really??
> >
> >
> >Chris, the behavior you describe is expected.  The point is that 13 to
>23
> >is one voltage plane in the board to another.
> >
> >I see that where we got skewed is that you wanted to relate the model
>back
> >to Doug's experiment.  I took Doug's results for granted and was not
>trying
> >to reproduce them.
> >
> >If we want to make this model reproduce Doug's experiment, then I
>contend
> >we want to replicate the network multiple times.  That would give us a
> >little bed spring model.  In the single bonding case, remove all CYx
>except
> >for CY1, and CY2.  In the multiple bonding case, populate all CYx.  If
>you
> >prefer to use an R/L network in place of each CYx, I contend it makes
>no
> >difference at the frequencies of interest.  If we extend the model this
> >way, then I maintain we will both see Doug's results, as well as be
>able to
> >evaluate the plane capacitance represented by CX.  So, I contend that
>by we
> >can show the situations Mike describes that he has successfully triaged
> >with BC.  And better yet, I contend we can establish models that tell
>us
> >how much chassis bonding to trade-off, so that BC is not necessary in
>the
> >first place.
> >
> >What do you think?
> >
> >Regards,
> >
> >
> >Steve.
> >At 02:06 PM 3/17/2004 -0800, Chris Cheng wrote:
> > >Steve,
> > >I would have to disagree. If I take you model and make the impedance
> >between
> > >23 and 0 smaller (either by making CY2 very big or a parallel shunt
>Rs with
> > >very small value), the noise across CX actually increases. Clearly
>that's
> > >not the case in Doug's experiment. Remember, the shunting can only be
>done
> > >asymmetrically on either 23 or 13 (i.e. he can only shunt one node to
> > >chassis but not both) and yet this asymmetrical shunt causes a
>dramatic
> > >decrease in differential noise between 23 and 13 (at least in some
>area of
> > >the PCB). That's why I believe the noise injection is skew towards
>one side
> > >and bleeding it through the chassis give you a better bang for the
>buck (no
> > >need to add planes).
> > >
> > >-----Original Message-----
> > >From: steve weir [mailto:weirsp@xxxxxxxxxx]
> > >Sent: Tuesday, March 16, 2004 4:25 PM
> > >To: Chris.Cheng@xxxxxxxxxxxx; Chris Cheng; 'si-list@xxxxxxxxxxxxx'
> > >Subject: Re: [SI-LIST] Re: ESD is a low frequency event -really??
> > >
> > >
> > >Chris, no problem.  I think that we are both looking at the chassis
>as a
> > >big shunt, but have expressed it differently.  The line to chassis
>ground
> > >connections in my case are  CY1, CY2.  Since ESD is not DC, the fact
>that
> > >CY1 and CY2 block DC doesn't matter, just make the capacitances
> > >large.  They are non-ideal capacitors, so they each have the
>equivalent of
> > >( Rshunt + R3 + Lshunt + L3 )/2 that you propose.  It's pretty much
>just a
> > >different way of organizing the network into a familiar form.  The
>one
> > >objection that I do have is the noise injection at 23 instead of 1.
>My
> > >rationale for injecting at 1 is that from a distance the power and
>ground
> > >planes were very similar but not perfectly matched to the noise
> > >source.  Alternately we could make either R1 or R2 an open and inject
>into
> > >node 1.
> > >
> > >Now, let's see what happens in both cases.
> > >
> > >First, without a connections to a low inductance chassis,
>differential
> > >conversion is limited by CX.  So, I think that we agree on the value
>of
> > >frequent, low impedance chassis connections.
> > >
> > >Second, unequal impedance between L2 and the shunt path
>Lshunt/Rshunt/L3/R3
> > >in your model, or CY1, CY2 in my model both lead to differential
>voltage
> > >across 12 to 22  and 13 to 23, that CX reduces.
> > >
> > >Are we in agreement so far?
> > >
> > >Regards,
> > >
> > >
> > >Steve.
> > >
> > >
> > >
> > >At 03:43 PM 3/16/2004 -0800, Chris Cheng wrote:
> > > >Sorry Lshunt should be 23a 23 not 13a 23
> > > >
> > > >-----Original Message-----
> > > >From: Chris Cheng
> > > >Sent: Tuesday, March 16, 2004 3:37 PM
> > > >To: 'steve weir'; Chris Cheng; 'si-list@xxxxxxxxxxxxx'
> > > >Subject: RE: [SI-LIST] Re: ESD is a low frequency event -really??
> > > >
> > > >
> > > >Steve,
> > > >I would propose modifying your circuit a little bit,
> > > >
> > > >vsource 1 0
> > > >
> > > >R1 1 12
> > > >L1 12 13
> > > >CX 13 23
> > > >* remove CY1 13 0
> > > >
> > > >R2 1 22
> > > >L2 22 23
> > > >* remove CY2 23 0
> > > >
> > > >
> > > >*add the following
> > > >R3 1 32
> > > >L3 32 33
> > > >
> > > >Inoise 23 0
> > > >
> > > >Rshunt 33 23a
> > > >Lshunt 23a 23
> > > >
> > > >The R3/L3 represent the chassis and the Inoise is the ESD discharge
> > >injected
> > > >into the logic ground branch.
> > > >The question then becomes whether making the Rshunt/Lshunt very
>small
> >(dead
> > > >shorts between chassis and logic ground) and R3/L3 very small
>(gigantic
> > > >chassis metal cage vs. copper PCB planes) makes the differential
>noise
> > > >between 23 and 13 even smaller by steering the current through
>branch
> >R3/L3
> > > >instead of R1/L1 and CX.
> > > >
> > > >What do you think ?
> > > >
> > > >-----Original Message-----
> > > >From: steve weir [mailto:weirsp@xxxxxxxxxx]
> > > >Sent: Tuesday, March 16, 2004 2:14 PM
> > > >To: Chris.Cheng@xxxxxxxxxxxx; 'si-list@xxxxxxxxxxxxx'
> > > >Subject: Re: [SI-LIST] Re: ESD is a low frequency event -really??
> > > >
> > > >
> > > >Chris, I agree with most of your points here.  The way that I look
>at
> >this
> > > >problem is as a network of parallel LC shunts between the PCB
>planes,
> >both
> > > >power and ground and the chassis.  So, definitely I agree that more
> >shunts
> > > >will do a better job of limiting differential potential.
> > > >
> > > >The behavior of the BC is to shunt between those networks.  You can
>run a
> > > >very quick SPICE model by taking three non-ideal capacitors in a
>classic
> > > >line to line and line to ground ( ie X + 2Y ) filter configuration,
>and
> > > >tolerance the values.  In our case the X capacitor is the BC.
>Place an
> > > >impedance, resistive and/or inductive in series with each line and
>then
> > > >monitor both the CMV, and the DMV across frequency for a noise
>source fed
> > > >into both of the impedances:
> > > >
> > > >vsource 1 0
> > > >
> > > >R1 1 12
> > > >L1 12 13
> > > >CX 13 23
> > > >CY1 13 0
> > > >
> > > >R2 1 22
> > > >L2 22 23
> > > >CY2 23 0
> > > >
> > > >The common mode voltage may be observed at either node 13, or 23.
>The
> > > >differential mode is across 13 and 23.  Imagine 13 as a point on a
> >voltage
> > > >plane and 23 as a nearby point on a ground plane.
> > > >
> > > >Now, if we make CX really small, then the matching of the LPF
>networks
> > > >determines the differential mode conversion.  By increasing the
>value of
> > > >the X capacitor, we can swamp out the differences and greatly
>improve the
> > > >common mode to differential conversion caused by the network
>mismatches,
> > > >which is to say our immunity.
> > > >
> > > >But how much improvement do we need over ordinary dielectric and
>when?  I
> > > >would like to figure out for myself if and when high cost BC is
>justified
> > > >at design-time as opposed to as a big band-aid for a customer who
>can't
> > > >ship an improperly designed product.  I don't personally know the
>answer,
> > > >and was hoping that Mike would provide some numbers or more
>specific
> > > >examples.
> > > >
> > > >Regards,
> > > >
> > > >
> > > >Steve.
> > > >
>
>
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Steve Weir
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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Teraspeed(SM) is the service mark of Teraspeed Consulting Group LLC


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