[SI-LIST] Re: ESD is a low frequency event -really??
- From: MikonCons@xxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 12 Mar 2004 18:38:53 EST
Chris:
It appears some misinterpretations and "out of context" conditions have crept
into this discussion. A clarification appears to be needed as to my
statements. First I need to reiterate some text from my initial comments on
this thread
as follows.
*
"Unfortunately, there is no single magic bullet of design techniques for the
wide range of ESD strike characteristics. However, I have achieved
considerable success using multiple-layer, via-interconnected (staggered via
spacings),
chassis ground rings on the periphery of printed circuit boards (PCBs)." (Note
the reference to chassis ground rings, which I clarified in an earlier note,
see below.)
********
Your comments: (Two separate ones)
My take on the experiment is,
a) You may think your isolation between chassis and logic ground can nicely
control your discharge path from the critical circuit, but the reality is noise
may still get on the logic planes and by limiting the coupling between
chassis and logic ground (like your proud isolated chassis ground ring rather
than
solid connection between logic and chassis), you have generate excessive CMV
noise than normal.
b) Multiple logic to chassis connections provide the lowest CMV disturbence
to the logic planes. What is needed to be done is take care on not placing
critical component near where the real chassis ground return to earth.... And,
What remains is the possiblility of localized CMV that can somehow get
injected into your critical package instead of returning to the chassis
discharge
path. After reading Doug Smith's Tech tidbit
http://emcesd.com/tt2002/tt050102.htm as a follow up of this thread, I am
starting to question your practice of
isolating chassis ground without tight couple to logic ground. I think it will
result in the excessive CMV generate on the logic ground plane and thereby
needing the addition of BC just to bring down the ripple. I have stated my
suspicious before whether maximum isolation between chassis ground and logic
ground
makes sense. And Doug's experiment confirm my doubt.
*
And,
*
Once again, I have no religion on isolate or connecting chassis and logic
ground but my preference will be multiple connections around the PCB since I
believe a lot of PCI cards or disk drives has it shorted internally anyways. I
have tested both cases and they don't make any difference to my systems.
********
My prior comments:
My concept for the use of ground rings includes the provision of a low
impedance current path isolated from and surrounding the main PCB circuits.
This
represents a sacrificial intercepting structure that will divert the primary
current flow from an ESD strike via the lowest impedance path (always preferred
in
the natural world) to the main structure, and then to earth.....
*
And in a followup note,
*
Specifically, I did not mean to imply that one must not connect the chassis
ground rings to the signal ground on the board. Generally this connection is
done at critical interfaces (high-speed data signals and/or power return
interfaces) and may be done at more than one location. The voltage caused by an
ESD
strike is rendered to be common-mode voltage to the operational circuits at
that/these connection point(s). The connection should be a low inductance
connection.
For the case where a large PCB is used (a motherboard is a common example),
there may be many structural mounting points for the PCB. Many vendors take
advantage of these extra chassis ground points to create a local "quiet ground"
by connecting signal and chassis grounds together. Several years ago, MIPS
computers were shining examples of this technique.
********
Your comment:
If it is indeed what you said below that BC only improves the margin on a
properly stackup PCB. I would suggest a better margin can be achieve even
without
BC by simply removing your oh so proud isolated chassis ring and have direct
tight connection between chassis and logic reference on PCB.
********
My prior comment:
Perhaps the explanation I offered was not explicit enough for you. The "50-60
different designs" I referred to had ESD susceptibilities and yes, some of
them were not well layed out to start with; however, even well designed boards
improved their margins of susceptibility using BC construction. (NOTE: The
"well layed out" boards were improved by the use of BC With or WITHOUT chassis
ground rings.)
********
Your latest comments:
I think the timing of contributing comments on this thread is nicely coming
together. So let's see what we have so far :
a) Not well design stackup, fix the stackup instead of using BC
b) I/O failure, tighten your signal reference is always more effective then
using BC
c) Discharge through package, nothing you can do on PCB even with BC
*********
And my response:
Item (c): We have already agreed on this as I stated in one of my earlier
comments, "As for your "core power distribution case" and "discharge happens
through your package," I agree that BC (or few if any other techniques) will
correct a design that places PCB-mounted components in (ESD) harms way."
Item (b): I have made no claims that BC helps well designed signal paths;
however, BC can indeed improve performance in those signal routings where the
signal path transitions layers to the opposite side of a BC sandwich without
the
potential need for added return current vias (that are not always required). I
do maintain that any common-mode coupling to the board, and from there to the
signal traces, is better balanced with a properly designed BC board.
Item (a): Depends on what needs fixing, if anything. My premise is that BC
provides benefits over a broad frequency range in PDS design, and helps to
minimize IC common-mode susceptibility (if properly incorporated of course).
The
drawback is (naturally) higher cost than a non-BC board, assuming that all
other
functional design performance requirements can be met with a non-BC board.
And, I have found BC improves the margin of susceptibility to ESD events
through
low-Q, tightly coupled power/ground planes to the multi-GHz region.
NOTE: I do not use BC indiscriminately on all board designs. Sensitive cost
factors, the performance requirements, and the packaging environment dictate my
choices. Where the requirements are paramount, I do use BC with at least two
sandwiches in a balanced PCB layup. Similarly, I use chassis ground rings
where ESD or radiated emissions performance needs as great a margin as is
reasonable.
Every design and each different application has unique requirements that
dictate the prudent choice of adequate design techniques. The design task is to
apply the right ones, alone or in combination, to achieve the desired result.
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: (408)821-9843
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