[SI-LIST] Re: ESD is a low frequency event -really??
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: "'MikonCons@xxxxxxx'" <MikonCons@xxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 12 Mar 2004 12:56:11 -0800
I think the timing of contributing comments on this
thread is nicely coming together.
So let's see what we have so far :
a) Not well design stackup, fix the stackup
instead of using BC
b) I/O failure, tighten your signal reference is
always more effective then using BC
c) Discharge through package, nothing you can do
on PCB even with BC
What remains is the possiblility of localized CMV
that can somehow get injected into your critical
package instead of returning to the chassis
discharge path.
After reading Doug Smith's Tech tidbit
http://emcesd.com/tt2002/tt050102.htm as a follow up
of this thread, I am starting to question your
practice of isolating chassis ground without tight
couple to logic ground.
I think it will result in the excessive CMV generate
on the logic ground plane and thereby needing the
addition of BC just to bring down the ripple.
I have stated my suspicious before whether maximum
isolation between chassis ground and logic ground
makes sense. And Doug's experiment confirm my doubt.
My take on the experiment is,
a) You may think your isolation between chassis and
logic ground can nicely control your discharge path
from the critical circuit, but the reality is noise
may still get on the logic planes and by limiting
the coupling between chassis and logic ground (like
your proud isolated chassis ground ring rather than
solid connection between logic and chassis), you
have generate excessive CMV noise than normal.
b) Multiple logic to chassis connections provide
the lowest CMV disturbence to the logic planes.
What is needed to be done is take care on not
placing critical component near where the real
chassis ground return to earth.
If it is indeed what you said below that BC only
improves the margin on a properly stackup PCB.
I would suggest a better margin can be achieve
even without BC by simply removing your oh so
proud isolated chassis ring and have direct
tight connection between chassis and logic
reference on PCB.
I believe the same <100MHz choke point due to
package parasistics that prevents your high
speed on board decoupling current can help
your die will limit the noise that
can inject your localized CMV to the die.
The real low impedance path you want to
provide is the shortest way to allow the
current to flow away from the board and
towards the chassis (multiple tight coupling).
I think a better cause of action seems to
be throwing away your isolated rings and BC
and don't put your critical components near
a potential discharge path.
-----Original Message-----
From: MikonCons@xxxxxxx
To: si-list@xxxxxxxxxxxxx
Sent: 3/11/2004 2:46 PM
Subject: [SI-LIST] Re: ESD is a low frequency event -really??
In a message dated 3/10/2004 4:01:36 PM Pacific Standard Time,
Chris.Cheng@xxxxxxxxxxxx writes:
No real data/example, still speculation.
You can't just say I've done it 35 years therefore it must be correct if
you
can't even tell me there is a single case where a properly stackup PCB
without BC will fail ESD test and after adding BC it works. This is a
simple
yes or no answer, nothing proprietary about it.
I am still waiting.
****************
Chris: Two items follow.
1. Perhaps the explanation I offered was not explicit enough for you.
The
"50-60 different designs" I referred to had ESD susceptibilities and
yes, some of
them were not well layed out to start with; however, even well designed
boards improved their margins of susceptibility using BC construction.
2. As for your "core power distribution case" and "discharge happens
through
your package," I agree that BC (or few if any other techniques) will
correct a
design that places PCB-mounted components in (ESD) harms way. None of my
earlier comments implied that BC alone was a panacea for ESD problem
correction. I
do maintain that use of BC is an excellent tool for minimizing the
disruptive
effects of any high-frequency injection of common-mode voltage on a
power
distribution system (PDS). Since the electrical environment for
operational
circuits AND their interconnects which use power or ground as reference
planes (as
any good designer would) is formulated by the PDS, CMV bursts are
mitigated to
a substantial degree.
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: (408)821-9843
*** Serving Your Needs with Technical Excellence ***
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
