[SI-LIST] Re: ESD is a low frequency event -really??
- From: Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 8 Mar 2004 17:18:42 -0800
Once again, I have no religion on isolate or connecting chassis and logic
ground but my preference will be multiple connections around the PCB since I
believe a lot of PCI cards or disk drives has it shorted internally anyways.
I have tested both cases and they don't make any difference to my systems.
I also understand why all those classical/conventional single point
connection came from as describe below. The purpose is to control the
leakage point so that the harmful current will not disrupt the critical
circuits operating deep inside the PCB. However, after the ESD induced
failure on a server clock board I quoted in previous thread and some
observations on newly developed systems, I begin to have second thoughts on
these single point contact or isolation rings. The problem with the old
school thinking is it is really assuming the ESD discharge can only happen
on the peripheral of the PCB. It assumes by isolating the peripheral of the
PCB, the discharge current will be forced to flow along the edge of the PCB.
This is probably true for old style enclosures with lots of space between
the PCB and the enclosure on top and little or no metallic structure at the
bottom. This is not the case for all these newer 1U,2U server blades or high
wattage PC with Manhattan sky scraper heat sinks or air duck/baffles. The
seperation between these metal objects and the enclosure is close enough to
become the preferential discharge path if the peripheral of the PCB is
completely isolated except for a single point or none. I believe that's what
happened in the clock board example I quoted because the board was oriented
sideways with the metal can of the oscillator very close to the gasket on
the side. In these cases, think 3D instead of 2D and it makes sense to tie
the board gnd to the chassis in as many points as you can do just to avoid
the zap takes the path through the heat sink of some critical components.
As for the BC comment, beside it being speculative, I can also make the top
and bottom reference planes to be ground and therefore don't need any plane
capacitance to provide the surface current to discharge.
-----Original Message-----
From: MikonCons@xxxxxxx [mailto:MikonCons@xxxxxxx]
Sent: Friday, March 05, 2004 3:25 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: ESD is a low frequency event -really??
Gentlemen:
I apologize for the length of this dissertation, but I hope it may clear up
a
few seemingly disparate positions opined by others earlier, as well as
stimulate some more in-depth thought.
As pointed out earlier, ESD is a complex phenomena to model. The results and
impacts observed will be radically different depending on the initial charge
voltage, rates of closure between the arc points, and total physical
structure/configuration of the two participating "bodies" involved.
That being acknowledged, about four years ago, I attended an EMC Society
presentation (Santa Clara, CA, sorry, don't recall who presented) where
multiple,
carefully planned and conducted ESD test results were presented. The test
items were enclosed in a shielded enclosure to minimize coupling (false)
effects
on the high-speed oscilloscope probes and cables. The most enlightening
findings were that the lower voltages (4k-8k volts) produced rise times in
the few
picoseconds range (yes, picoseconds). The higher voltages (30k-50k volts)
produced much slower rise times (a factor of ~10 as I recall), probably
because of
the longer and more lossy arc path associated with these voltages. The
higher
voltage arcs contained significantly more energy (1/2*C*V^2) and were
delivered
through a longer (higher inductance) and more resistive path; therefore,
slower rise times, longer discharge durations, and correspondingly lower
frequency
content were observed for these strikes before the arc quenched.
Bottom line: It is nonsense if one does NOT think that many (lower voltage)
ESD events do not contain GHz frequency content with all its negative
interference effects. Conversely, very strong low frequency energy content
will be
observed in higher voltage ESD events. The latter case has particularly
nasty
magnetic coupling affects.
THE FIX:
Unfortunately, there is no single magic bullet of design techniques for the
wide range of ESD strike characteristics. However, I have achieved
considerable
success using multiple-layer, via-interconnected (staggered via spacings),
chassis ground rings on the periphery of printed circuit boards (PCBs). I
have
even used sharp points on the outboard edges of the rings to offer
"preferred"
ESD strike points to protect PCB operational circuits from taking the hit.
Some members of the SI List have scoffed at chassis ground rings (which I
introduced in 1989 with no prior knowledge that anyone else was using same);
therefore, you are free to dissent with me on their value. And clearly,
their use in
fully enclosed assemblies (as opposed to portable equipment or open
enclosure
"windows") is not normally necessary as such packaging is not conducive to
ESD
strike conditions.
HOWEVER...
My concept for the use of ground rings includes the provision of a low
impedance current path isolated from and surrounding the main PCB circuits.
This
represents a sacrificial intercepting structure that will divert the primary
current flow from an ESD strike via the lowest impedance path (always
preferred in
the natural world) to the main structure, and then to earth. Further, the
nature of the surrounding ring tends to divide the strike current so that a
180
degree phase relationship for the resulting strong magnetic fields is
created.
Circuits that are a few centimeters away experience canceling magnetic
fields
from the two segments of the ESD current. The circuits on each side of and
more near the strike point edge still experience strong fields, but they are
reduced (as a minimum) in proportion to the division of strike current flow
in the
opposite directions along the chassis ground rings; i.e., by at least 6 dB.
Other ESD hardening techniques that should be considered in conjunction with
the use of chassis ground rings include (a) using buried/stripline traces,
(b)
NOT routing critical traces along PCB edges (on any layer), and (c)
maintaining a continuous signal ground (generally part of a plane) around
the PCB
periphery (isolated from the chassis ground ring). For superior performance,
the
ground plane should be tightly coupled to the power plane(s) as well.
In my experience on redesigns of deficient PCBs where I incorporated the
above noted features, the chassis ground ring structure demonstrated a
diversion
of at least 95% (typically >=99%) of the ESD energy away from the
operational
PCB circuits. Item (a) inherently provides shielding generally in excess of
20
dB. Item (b) minimizes any E- and H-field coupling to the trace through
spacing. Item (c) will absorb coupled energy in a manner that presents
common-mode
voltage to the PCB circuits which then tends to be rejected. This result
depends on the tight power/ground plane coupling noted earlier, which is why
I also
strongly urge the use of buried capacitance (BC) power distribution designs.
Note also that the magnetic coupling in item (c) will tend to cancel in
proportion to the ESD directional/opposite current division in the chassis
ground
rings; therefore, the coupling mechanism is primarily via capacitively
coupled
E-field between the rings and the ground plane. Note also that the multiple
paralleled chassis ground rings provide a very low impedance (both low
inductance
and low resistance) to the ESD current, thereby minimizing the E-field
strength. All of the above contributes to the robustness of a given design.
As a further effect that has not been fully understood (or publicized), the
use of BC planes is very beneficial in extending the common-mode voltage
coupling characteristic of item (c) out to very high frequencies (GHz
region).
Hence, BC provides reduced circuit susceptibility to ESD events even into
the
multi-GHz region.
GENERAL COMMENTS:
Most PCB designs have unique physical and electrical characteristics;
therefore, every Engineer/Designer should think for themselves as to the
design
risk/environment for ESD and think out the proper mitigation techniques. One
should
know WHY a specific technique is used based on electromagnetic principles.
If
one cannot understand the WHY, more education is required, or another
vocation is in order. And lastly, please note that many design techniques
are
supportive to other techniques. If one designs for critical applications
(space
systems, military, life-threatening, and other man-rated systems as I do),
it is
better to initially design in extra margins of safety through the use of
several
complementary techniques, and then (when successful) look to the second
generation design for value/cost-engineering modifications.
Respectfully,
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: (408)821-9843
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