[SI-LIST] Re: EMC
- From: "Suresh.K" <sureshk@xxxxxxxxxxxxxx>
- To: subramani <subbu@xxxxxxxxxxxxxxxxxxx>
- Date: Wed, 5 Nov 2003 12:54:21 +0500 (GMT+0500)
Dear Sir,
According to your Board Stack you have two strip lines and one
assymmetrical dual stripline,but the two strip lines are bounded by one
side power plane and Ground Plane on the other side......
If you have both side ground plane reference for the strip lines ,you can
route all the Impedance controlled signals on Layer2 & layer8,because
strip lines bounded by ground planes will be best layer for better signal
integrity.
But now you have assymmetrical dual stripline bounded by ground planes,so
I beleive that layer 5&6 may be better option for routing clock
signals,which will useful for return path, but you need to care of tandem
pair of traces.
and regarding board power plane EMI,you can follow 20H rule on layer2&
layer9 power planes to reduce the power plane EMI and Top & Bottom layers
you are doing Ground fill, so I think the device EMI will be controlled by
the Ground fills.
Regards,
Suresh.K,
Vth EDA Lab,
C-DOT,
Bangalore-52.
On Wed, 5 Nov 2003, subramani wrote:
> Hello,
>
> I am doing a board design. It has to pass stringent EMI tests.
>
> Mine is a 10 layer board.
>
> The board stack up is
> 1 TOP component, GND filling
> 2 Power
> 3 signal
> 4 GND filling
> 5 signal
> 6 Signal
> 7 GND filling
> 8 Signal
> 9 Power
> 10 Bottom Component, GND filling
>
> The board has SDRAM operating at 100Mhz. Where should I route the clocks.
> Could anyone tell me about the ways and means of reducing EMI.
> The SDRAM is placed that is near to the edge of PCB. Will it cause
> radiation.
> Is there a formula for keepout distance.
>
> Regards
> Subramani
> Mistral
>
>
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