[SI-LIST] EMC
- From: "subramani" <subbu@xxxxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 5 Nov 2003 11:45:17 +0530
Hello,
I am doing a board design. It has to pass stringent EMI tests.
Mine is a 10 layer board.
The board stack up is
1 TOP component, GND filling
2 Power
3 signal
4 GND filling
5 signal
6 Signal
7 GND filling
8 Signal
9 Power
10 Bottom Component, GND filling
The board has SDRAM operating at 100Mhz. Where should I route the clocks.
Could anyone tell me about the ways and means of reducing EMI.
The SDRAM is placed that is near to the edge of PCB. Will it cause
radiation.
Is there a formula for keepout distance.
Regards
Subramani
Mistral
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