[SI-LIST] Driver impedance, slew rate, loading and signal integrity

Hi, folks:
 
   I've been doing some study on DDR3 output driver design. The driver is 
driving a multi-drop ( DRAM units) channel with far-end resistive termination 
to VTT(VDD/2). 
 
   JEDEC spec defines different output driver impedance for different No. of 
loading DRAM units. For example, the more units are loaded, the lower the 
output impedance will be configured.
 
   My question is that the slew rate of the driver should be faster or slower 
for heavy loading? 
 
   The trade off is between larger eye opening and reflection (from fast edge 
rate). I wish to hear SI experts' idea and welcome literature/emperical inputs.
 
Thanks.
Neo
 
 
 

      
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