[SI-LIST] Doubt in SSTL_18 dc specPRA

Hi all,
While going thro the SSTL_18 JEDEC spec I came across a conclusion.
Could someone comment on it?
The conclusion is as follows:
While interfacing with DDR2 memories, the maximum external resistor (used for 
termination, slew rate control etc)
value should be less than or equal to 30.56ohms for meeting dc specs.

How I concluded it?
1. The minimum current (Imin) sourced/sinked by the 
I/O buffer (for e.g Processor) to maintain Voh/l(dc)(min) is +_13.4mA. [from 
JEDEC]
2. The maximum on resistance (Rn/pmos) of N/PMOS is 21ohms. [from JEDEC]
3. I(min) = [Vddq(min)-VTT(max)]/(Rn/pmos + Rext)
==>  13.4mA=[1.7-(0.969+40)]/(21+Rext)
4. This gives Rext=30.56ohms.

Regards
Canes





      5, 50, 500, 5000 - Store N number of mails in your inbox. Go to 
http://help.yahoo.com/l/in/yahoo/mail/yahoomail/tools/tools-08.html
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: