[SI-LIST] Re: Dividing a low jitter clock by 2

This is not directly applicable to Marc's situation but close enough that I
thought I'd share it. I'm currently working on a design involving a PLL that
synthesizes the RF carrier for a satellite modem. The phase noise
requirements are extremely tight. An FPGA is involved to tune the PLL (a
Hittite fractional-N synthesizer chip) and control a bunch of filters, etc.,
but the initial design also used the FPGA to divide a clock and do some
muxing to select the reference clock for the PLL. The FPGA does not use a
PLL internally - just flip flops and gates to divide and mux the reference
clock. So you would not expect the FPGA to inject a lot of noise. But it
ended up that the miniscule amount of phase noise the FPGA did introduce
resulted in a 10 dB degradation in the phase noise on the RF carrier out of
the PLL (in the GHz range). We are now moving those dividers and muxes to
discrete logic outside the FPGA.

This is one of those things that was impossible to quantify beforehand.
There are no data to base the analysis on. You just have to try it and see
how it turns outs. We're pretty confident that the external logic will do
the trick (this is more along the lines of Marc's original question). As a
side note, the clock we're dividing is between 150-200MHz and we have to do
a /3, which requires both edges of the clock to fix the duty cycle. So the
flip-flops need to be rated for well over 300MHz. This is basically
impossible to do with any discrete CMOS logic family. But we came across a
new company called Potato Semiconductor (potato chips - get it?), who make
an incredible CMOS logic family they call "GHz 74 Series Logic". Thought I'd
toss that out there because nobody I've mentioned this to has heard of
Potato Semi.

Good luck, Marc. I agree with your approach below.

Bob S.

> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx 
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Marc Battyani
> Sent: Saturday, January 31, 2009 1:09 PM
> To: SI-List
> Subject: [SI-LIST] Re: Dividing a low jitter clock by 2
> 
>  Thanks to all,
> Finally it seems that the FPGA can generate all the 
> frequencies it needs froma 25MHz input instead of a 40MHz one 
> so we can get rid of that frequency output on the PLL and 
> don't need to divide by 2 anymore.
> It's probably the safest way to do that :)
> 
> Marc
> 

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