[SI-LIST] Re: Dividing a low jitter clock by 2

 Thanks to all,
Finally it seems that the FPGA can generate all the frequencies it needs
froma 25MHz input instead of a 40MHz one so we can get rid of that frequency
output on the PLL and don't need to divide by 2 anymore.
It's probably the safest way to do that :)

Marc

todd t wrote: how about making 25MHz with the PLL and use the clk resources
in the FPGAs to make 50 (and 40) internally?  I'm personally against the
logic divider for tight jitter requirements. it's an additional stage that
has no jitter reduction and is just going to be susceptible. have you found
a1.8V divider with a narrow zone between Vil-max and Vih-min?  there's no
guarantee the device will switch at the same voltage every cycle, although
granted there won't be temperature or voltage (or process) changes that will
be large one cycle to the next. but still. maybe find a better PLL with more
outputs? 

sorry to put doubts in your head when the general consensus has been the
other way. but I'd consider other options personally before committing. 


-todd tamas 

On Jan 31, 2009, at 2:46 PM, Marc Battyani
<marc.battyani@xxxxxxxxxxxxxxxxxx>[1]wrote: 

Thanks to all for your replies. 
The application is Synchronous Ethernet. (ITU-T G.8262) 

The synchronized PLL clock has a jitter of 0.3ps rms and I need 25MHz for 
thePHY as well as 40MHz and 50MHz for the FPGAs. The PLL I plan to use 
(SI5326) only has 2 clock outputs so I would like to divide the 50MHz on one

output by 2 to get the 25MHz clock and output 40MHz on the other one. 
For the divider I'm thinking of using is a single gate flipflop like this 
one(at 1.8V): 
http://www.standardics.nxp.com/products/aup/datasheet/74aup1g79.pdf[2][1] 

Marc 

Peter zhu wrote: Marc: As my experience, clock jitter is determined by the 
source clock. In theory, simple sequential or combinational logic will no 
introduce jitter. In one of our high-precise telecom clock board design, we 
use a low-jitter temperature-compensate OSC, but we use a general CPLD to 
generate other clocks with different freq. Keep an eye on using PLL, because

your jitter will be determinded by ths PLL after you clock go through this 
PLL. Peter zhu Emerson Network Power On Sat, Jan 31, 2009 at 12:10 PM, 
Mikhail Matusov <matusov@xxxxxxxxxxxx>[3][2]wrote: Marc, You need to tell us

what low means and you need to understand how much jitter you can actually 
afford. Besides jitter you have to consider clock skew you will be 
introducing. /Mikhail ----- Original Message ----- From: "Marc Battyani" 
<marc.battyani@xxxxxxxxxxxxxxxxxx>[4][3] To: "SI-List" 
<si-list@xxxxxxxxxxxxx>[5][4]Sent: Friday, January 30, 2009 5:44 PM Subject:

[SI-LIST] Dividing a low jitter clock by 2 >Hello, I have a design with a 
lowjitter reference clock at 50MHz. I would like to divide it by 2 but 
without adding much jitter. Can I do that with a $0.40 D flipflop gate or do

I really need a low jitter PLL? I think the flipflop can degrade the cyclic 
ratio and add some unknown delay but I don't see why it would degrade the 
jitter performance. Am I to optimistic? The signals are 1.8V CMOS. Thanks, 
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