[SI-LIST] Re: Dividing a low jitter clock by 2

As this is a noninverting D flip-flop, you will of course need to add an
inverting buffer.  The characteristics of that buffer are mostly unimportant
because they mostly don't affect the jitter at the FF's Q output.  But it
does mean routing the FF output to at least two destinations (the inverter,
and your load), which means being watchful for plateaus on that waveform,
which could cause increased jitter, or double-clocking.


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