[SI-LIST] Re: Dividing a low jitter clock by 2

Seems to me, the only jitter added to a clock by a digital divide-by-2
circuit, would be due to delay time uncertainty, plus noise and crosstalk
into your circuitry ... whether into the signals, the supplies, or the
transistors themselves (common die with other circuits).

A sloppy flip-flop (if such a thing exists in modern technologies) might
make it worse; one with a good snappy response should be better, all other
things being equal.  Keep the input signal fast and snappy, but controlled.
An IC technology where the delays change less vs. supply voltage might help
avert delay modulation as the supply fluctuates from noise on the VDD pin.
Bypass well.  If you use a separate IC, don't use the other D-flops or gates
in that IC for other (asynchronous) purposes.  Also pay attention to
terminations and reflections, since a reflection hitting the IC at the
moment it's flipping could influence its apparent switching point.

Andy

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