[SI-LIST] Re: Dividing a low jitter clock by 2

Marc,

You need to tell us what low means and you need to understand how much 
jitter you can actually afford. Besides jitter you have to consider clock 
skew you will be introducing.

/Mikhail



----- Original Message ----- 
From: "Marc Battyani" <marc.battyani@xxxxxxxxxxxxxxxxxx>
To: "SI-List" <si-list@xxxxxxxxxxxxx>
Sent: Friday, January 30, 2009 5:44 PM
Subject: [SI-LIST] Dividing a low jitter clock by 2


> Hello,
>
> I have a design with a low jitter reference clock at 50MHz. I would like
> to divide it by 2 but without adding much jitter.
> Can I do that with a $0.40 D flipflop gate or do I really need a low
> jitter PLL?
> I think the flipflop can degrade the cyclic ratio and add some unknown
> delay but I don't see why it would degrade the jitter performance.
> Am I to optimistic? The signals are 1.8V CMOS.
>
> Thanks,
>
> Marc
>
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