[SI-LIST] Re: Dividing a low jitter clock by 2

Hi Marc,
actually, dividing your frequency  by 2 with a flip-flop will IMPROVE (not 
degrade) your clock's duty cycle (I assume "dutyv cycle" is what you mean 
with "cyclic ratio"). Just imagine a 50 MHz clock with 30% positive duty 
cycle, i.e. 6ns high, 14ns low, and so on. Since the FF's output will only 
toggle with every rising clock edge, you'll get 20ns high, then 20ns later 
low, and so on, so your 30% duty cycle at 50 MHz has become exactly 50% at 
25 MHz.

How much jitter the flip-flop will add depends on a variety of parameters, 
among them the circuit architecture of the component (e.g. PECL devices 
tend to be much lower jitter than CMOS because they are geared towards 
higher-frequency applications), the stability and noise of your power 
supply (read: quality of your power decoupling), etc. First I'd have a 
look at the data sheet. Second, why not just try your $0.40 part and see 
how it work in your application - worst case you lost half an hour of your 
time and $0.40. It's not easy to give a definite answer since you did not 
tell us what your jitter requirements are ("low" can be 0.2ps RMS to one 
person and 2ps RM to another).

IMHO using a PLL for a straightforward divide-by-two is absolute overkill; 
not only much too complex, but also prone to adding more problems that you 
solve. You'd use a PLL if you'd either had to multiply the frequency (25 
MHz --> 50 MHz) or needed a non-intereg division ratio.

Wolfgang






Marc Battyani <marc.battyani@xxxxxxxxxxxxxxxxxx> 
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01/30/2009 02:44 PM

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[SI-LIST] Dividing a low jitter clock by 2






Hello,

I have a design with a low jitter reference clock at 50MHz. I would like
to divide it by 2 but without adding much jitter.
Can I do that with a $0.40 D flipflop gate or do I really need a low
jitter PLL?
I think the flipflop can degrade the cyclic ratio and add some unknown
delay but I don't see why it would degrade the jitter performance.
Am I to optimistic? The signals are 1.8V CMOS.

Thanks,

Marc

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