[SI-LIST] Re: Displaying eye pattern in an oscilloscope?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Ihsan Erdin <erdinih@xxxxxxxxx>
- Date: Sun, 23 Oct 2005 10:52:14 -0700
Ishan, what is the motivation for needing to know which memory device? We
have the controller sending data to store, and memory issuing read data
back to the controller. At one end of the bus or the other we want to know
whether the timing margins are adequate for each type of transaction. I
don't see a reason to care what read timing looks like except at the
controller, or what write timing looks like except at the memories. I see
visibility limited more by the physical accessibility than by anything else.
An eye is a way of getting information that embodies the various jitter
sources. An eye diagram can still be constructed by the method you suggest
by controlling the data patterns. Running DDR2, one might be well advised
to determine if either the channel, or the PDS induce substantial ISI.
Regards,
Steve.
At 11:13 AM 10/23/2005 -0400, Ihsan Erdin wrote:
>Hi Steve,
>
>I think a simulation vs. measurement comparison is the motivation behind
>the eye diagram capturing. I don't know what kind of post-processing
>filter you can apply to the captured waveform in order to eliminate one of
>the 90-degree apart strobe signals on a bi-directional bus but even if
>this were possible it would only work on a single memory interface. In
>order to understand which memory device is driving you still need to
>observe (trigger on) the /CS signal. All in all, I'm not convinced an
>eye-diagram scope capture is possible to form a reference to the
>simulation results. But if the idea is timing verification as you put it,
>yes, you can do that by probing (and logic triggering on) all the control
>signals but without an eyediagram pattern on the scope.
>
>Ihsan
>
>On 10/23/05, steve weir <<mailto:weirsi@xxxxxxxxxx>weirsi@xxxxxxxxxx> wrote:
>>Ishan, I do agree with you that just triggering on DQS and running
>>infinite persistence will just make an ugly mess on the screen. And if
>>what one wants to do is detailed characterizations by: target/source
>>DIMM, interleaved/non-interleaved bursts etc, what I suggest is inadequate.
>>
>>However, for the very same reason that infinite persistence without a
>>cycle type trigger doesn't work well, we can extract reads and writes
>>using only DQS and DQ. The trick is to use the 90 / 0 DQS to DQ phase
>>offset of write versus read as a post-process filter to separate out the
>>reads from the writes in .wfm captures. If the idea is to verify that
>>system level timing works, that should be enough for the data path. If
>>the skew moves around by more than 90 degrees such that reads can't be
>>distinguished from writes, then the channel is broken anyway.
>>
>>Regards,
>>
>>
>>Steve.
>>
>>At 11:14 PM 10/22/2005 -0400, Ihsan Erdin wrote:
>>>I'm not sure if it's possible at all. To capture a read or write cycle,
>>>you'll need a logic triggering setup for data and control signals (/WE,
>>>/CS) as Chris describes. For an eye diagram pattern, on the other hand,
>>>you'll need an edge trigger setup either at the clock or the data itself
>>>with a delay (one or two periods) A logic triggering with an infinite
>>>persistence display setting will not result an eye diagram.
>>>
>>>Ihsan Erdin
>>>
>>>On 10/22/05, Chris Cheng
>>><<mailto:Chris.Cheng@xxxxxxxxxxxx>Chris.Cheng@xxxxxxxxxxxx> wrote:
>>>>Not that simple.
>>>>You will most like need some advanced triggering to trigger on CAS, WE
>>>>so that you can tell if it is a read or write. Then you probably need
>>>>some software to limit the hit to certain address to be sure you get
>>>>the right DIMM. Good luck if you need to see the effect of interleave
>>>>vs. non-interleave.
>>>>________________________________
>>>>
>>>>From: <mailto:si-list-bounce@xxxxxxxxxxxxx>si-list-bounce@xxxxxxxxxxxxx
>>>>on behalf of steve weir
>>>>Sent: Fri 10/21/2005 10:59 PM
>>>>To: <mailto:rrepollo@xxxxxxxxxxxxxxxx>rrepollo@xxxxxxxxxxxxxxxx;
>>>><mailto:si-list@xxxxxxxxxxxxx>si-list@xxxxxxxxxxxxx
>>>>Subject: [SI-LIST] Re: Displaying eye pattern in an oscilloscope?
>>>>
>>>>
>>>>
>>>>Don't you have access to both clock and data?
>>>>
>>>>
>>>>Steve
>>>>At 09:17 AM 10/22/2005 +0800, Rep wrote:
>>>> >Good day!
>>>> >
>>>> >I simulated a data signal from SH4 processor to SDRAM, displaying it
>>>> in an
>>>> >eye pattern.
>>>> >I need to verify the signal by actual board evaluation.
>>>> >Could please someone tell me how I could measure the
>>>> >signal in eye pattern through the use of an oscilloscope (TEK)?
>>>> >
>>>> >I would really appreciated any help I could get.
>>>> >
>>>> >Thank you.
>>>> >
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