[SI-LIST] Re: Diff.Pairs


I've followed your emails exchanges with Mike Brown
closely.  This subject is a very important item as we
tackle high speed design using differential pairs.
Today, we have differential pair in CMOS logic,
LVDS, and differential HSTL (RLDRAM).

Both of you have argued with very good points and I
appreciated your thoughts.  But in this case, I would
side with what Lee has stated.  He may not have explicitly
stated the stackup in his assumption, but it is commonly
referred as the the broad side coupled differential pair
vs. edge coupled stripline differential pair.

There is no question about the benefits and level of
control from edge coupled differential where both tracks
are routed on the same layer.  But it is also very common
to have a dual stripline layers between two Ground layers
for broadside coupling.  This is mostly used in the backplane
side and have demonstrated success in many designs.

An example of this stackup can be:

=============   Ground plane for image return
                 Core, thickness H
     =====       Diff Layer #1
     =====       Diff Layer #2
                 Core, thickness H
=============   Ground plane for image return

I have been to a lot of seminar where SI experts argued
the Pro/Con of edge coupled vs. broadside coupled differential
pair. I have seen good results from both styles on frequency
under 3GHz.

Just my two cents,
Michael Chin

Scott McMorrow wrote:
> Mike
> That is my point.  This is an example of routing a differential pair 
> with matched skew, but on different layers. I do not recommend this 
> routing  at all.  It is, however an example of what Lee has advocated in 
> his post, which I quote here:
> "It is time to stop representing differential signals as needing to be
> tightly coupled to each other in order to operate properly.  It is simply
> not so.  I have routed thousands of differential signal where each member
> of the pair is on a different layer.  If this were not possible, 1 mm pitch 
> BGAs with differential signals would be un routable.  There are tens of
> thousands of such parts being shipped every month on PCBs where they are
> routed apart from each other. "
> This is an extremely bad practice and bad advice and should be shunned.
> regards,
> scott
> Mike Brown wrote:
>>Scott, the stackup shown has image current flowing in all 4 Pwr/Gnd 
>>planes for any signal transition, differential or common mode.  The only 
>>place where they cancel is at the driver's power/ground pins.  Noise on 
>>any of the planes will cause current flow in that plane pair; so to the 
>>extent that current in the plane can be considered common mode, you are 
>>correct.  I just do not see this stackup as being in any sense 
>>That it can be used to connect a differential driver to a differential 
>>receiver is true.  That it is in any way electrically optimal is false.  
>>That it may be the only route available may or may not be true.  The 
>>schedule would have to be extremely pressing for me to accept a board 
>>routed in this manner.
>>Scott McMorrow wrote:
>>>see below
>>>>how did the difference  between the noise voltages get to be common 
>>>>mode?  Given identical noise voltages on both traces, the difference 
>>>>is zero - and that is differential noise.  The CM noise is the 
>>>>average of the two noise voltages (sum/2) 
>>>I am talking about a case where Lee has suggested that the 
>>>differential pair can be split between two different routing layers.  
>>>The stackup might be as follows:
>>>diff layer 1
>>>Power 1
>>>diff Layer 2
>>>Power 2
>>>The noise on each of these layers is totally different.  Thus at any 
>>>point along the differential pair there is a common mode voltage 
>>>differential that occurs, causing a net current flow in one direction 
>>>or the other.  You are correct for signals that are referenced to the 
>>>same layer.
>>>Oh, and your point is well taken.  -1.5 dB of loss would be 1.5 dB of 
>>>gain.  Oops!

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