[SI-LIST] Dielectric strength

Hello All,
   I have few questions related to the creepage and clearance for any PCB 
dielectric  Although this is not a direct SI topic it does impact the 
performance of a system by constraining the spacings, layer assignments and 
layer count as well as many aspects that effect Signal 
integrity.  According to the spec IEC60950 (replacing UL1950), Section 
6.1.2 requires up to 1.5kV isolation for telecommunication networks to 
ground (or primary power).  If FR4 is assumed, with a dielectric strength 
roughly 1250kV/mil the calculation for the required thickness of FR4 is 
clear.  That is in the vertical direction of the PCB.  My question is 
directed at the lateral spacing for internal layers as well as external 
layers.  Since a PCB is laminated and not homogenous  I would expect the 
discharge path would along the interface boundary of the layers where the 
dielectric strength is compromized.  Is this a reasonable assumption? If 
so, what is the dielectric strength of this interface and what should the 
appropriate spacings be?  Secondly for outer layers either covered with 
solder mask or bare (in the case of a via) present a very different 
problem.  Again, I would expect the breakdown to occur along the interface 
for solder mask to PCB dielectric or through the open air for the exposed 
case.
What are peoples experiences and thoughts?

Regards
-Ed

  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               NORTH EAST SYSTEMS ASSOCIATES, INC
                             ------------------------------------- 

                         "High Performance Engineering & Design"
  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  Dr. Edward Sayre 3rd            e-mail: esayre3@xxxxxxxx
  NESA, Inc.                              http://www.nesa.com/
  5 Lan Drive, Suite 200          Tel  +1.978.392-8787 x 218
  Westford, MA 01886 USA       Fax +1.978.392-8686
  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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