[SI-LIST] Dielctric loss microstip/stripline

Why is the dielectric loss lower in microstrip compared to stripline?
   
  -Thanks
Ray Anderson <ray.anderson@xxxxxxxxxx> wrote:
  Forwarded to the list for Bob (rhaller@xxxxxxxxxxxxx)

-----Original Message-----
From: Haller, Robert [mailto:rhaller@xxxxxxxxxxxxx]=20
Sent: Monday, December 19, 2005 6:31 AM
To: ray.anderson
Subject: [SI-LIST] Re: Microstrip/Stripline

Ray Can you please post this to Si-list (until such time as we resolve
my posting issues)
----------------------------------------

This Micro-strip Strip-line thread is an interesting discussion that I
have previously pursued off-line with a few colleagues/list members. I
would love to see hard bench data that is a true apple to apples
comparison in time and frequency domains. =20

I have past experience in board shops and typical Micro-strip processes
do exhibit higher variations and until recently always preferred
stripline environments. But recent 2D/3D simulations have led me to
believe that Micro-strip can be designed to produce 'longer' working
links. =20

A number of folks I have discussed this issue with agree that=20
Microstrip usually has
Higher crosstalk=20
More difficult to control Z0=20
Lower dielectric losses (not including Solder mask)
Can avoid via stubs =20
Stripline usually has
Lower crosstalk
Homogenous environment (except for glass weave)
Higher dielectric losses
Via stubs

But what happens when you are routing high-speed differential networks
(Module and/or Backplanes) and you want to accurately compare theses 2
unique environments with similar routing densities.

Equivalent line widths/lengths between stripline and microstrip,
Microstrip with LPISM (Solder mask) and no via stubs, Microstrip
conductor shape not as well controlled.

Dual stripling - Single reference plane (second plane far away),
Stripline with Via stubs.

Regards, Bob

Robert Haller
Enterasys Networks
Core Routing - Hardware
Phone: 978-684-1340=20
FAX: 978-684-1499


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