[SI-LIST] Re: Designing PCB Stackups
- From: Eric Goodill <ericg@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 11 Dec 2008 11:14:44 -0800
Hi,
I've thought for years that there ought to be some kind of fairly standard
crosstalk coupon that the PCB mfg can test similar to the widely-used
impedance coupons. Every time I've brought it up, it seem that the expertise
on the production floor at the PCB mfg doesn't quite exist.
Is anybody regularly doing this?
-Eric
Lee Ritchey wrote: Istvan, I agree with your approach. Good fabricators
expect things to work this way. Lee [Original Message] From: Istvan Nagy
<buenos@xxxxxxxxxxx>[1] To: <codymiller@xxxxxxxxxx>[2];
<si-list@xxxxxxxxxxxxx>[3] Date: 12/10/2008 10:42:49 AM Subject: [SI-LIST]
Re: Designing PCB Stackups hi most of the people advices to not to specify
exact material types, leave this decision for the production people, based
oneveryday actual pricing and stock info. this way its cheapest to
manufacture, and the lead times are shortest. this is typical in the
industry. i dont advice this, because: crosstalk. if a production technician
adjusts layer thicknesses (chosing a different material) they can make the
original impedance values on the board, requested by the designer company,
but the crosstalk levels will change. this is something what a PCB
manufacturer and any of their employees can not understand, just a HW design
engineer or a signal integrity engineer. we had a processorboard, where the
manufacturer changed a dielectric layer from 50um to 75um, then the
impedances were correct, but the crosstalk levels (simulated) increased by
aroud 50%. what i would do, is to chose a pcb manufacturer, send a rough
stackup, ask if its ok for them or advice another stackup. then fix the
materials, and use those forever for that board, in its lifetime. managers
and purchasing people wouldnt like it, but thats the only way to have not
just controleld impedance, but controlled crosstalk levels as well. a common
misunderstanding in the industry, is that a lot of people specify
trace-to-trace clearances based on the trace width. (like d>2*w). it should
be specified based on the dielectric thickness (like d>2*h). if you
understand this, then its quite obvious why is it bad if the manufacturer
specifies/changes the thicknesses during production. the best is if you
calculate the impedances (you need a good field solver, like Polar-si8000 or
MMTL...), and check the resulting trace widths and dielectric thicknesses,
tosee if you can get good noise imunity and good circuit density on your
board. the first methos worked well 15 years ago when people had 2
controlledimpedance traces on a PCB, and it was easy to maintain proper
distance to other traces. if you check a DIMM memory module (you are from
Micron, wright?), its full of controlled impedance traces, closely spaced
because of the density. regards, Istvan Nagy Concurrent Technologies Plc, UK
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