[SI-LIST] Re: Designing PCB Stackups

  • From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
  • To: "steve weir" <weirsi@xxxxxxxxxx>, <codymiller@xxxxxxxxxx>
  • Date: Wed, 10 Dec 2008 11:12:52 -0700

Cody,
I ask the PCB vendor what they use for their standard FR4xx dielectric
constant, what the materials used are, etc.  If that works for the
application, that's what I use. Plain vanilla.  I typically design all
layers using the same dielectic constant because it's cheaper that way.
There are exceptions, but most of the time one size fits all.
What I am tight on is the final controlled impedance value.  I allow little
variation in the trace width on signal layers and the dielectric height is
also fixed (for signal or power).

Ken

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
Sent: Wednesday, December 10, 2008 7:21 AM
To: codymiller@xxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Designing PCB Stackups


cody, the best practices qualify specific materials for each layer, and
where possible specify more than one equivalent alternative.

Specifying materials only generically can leave your process control and
QA all over the map.  I strongly discourage that.

My $0.02.

Steve


codymiller@xxxxxxxxxx wrote:
> All,
>
> I have a general question regarding PCB stackup design. I am evaluating
> how we design our pcb stackups in our group now and I would like to put
> a procedure together or a set of rules of thumb to properly design a
> stackup. I would like the procedure to ask all the right questions up
> front.
>
> One question that came up is do PCB designers typically design with
> vendor specific materials in mind or do they design with generic prepreg
> and core materials. I see some pros and cons to both. What is typical in
> the industry.
>
> Any advice would be appreciated as well as if you know of any
> papers/resources on the web that could be helpful.
>
> Thanks,
> Cody
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