[SI-LIST] Design of op-amp

Hi all,
  I am trying to design a two-stage differential
op-amp. the first stage is differential amplifier with
inputs to PMOS's. The second stage is simple cs stage
amplifier.  
  The main problem is the gain of 1st stage. I get a
gain of just 30db while I may be needing more than
40db gain. On performing DC analysis I find all MOS in
saturation and input PMOS have enough room for voltage
swing. Moreover using the node voltages I get from the
analysis, I calculated the gain of 1st stage
approx(gm*ro/2) to about 45db. However simulation
results does not yield the same. How do i correlate
these two.
  Also how do i improve the gain of Ist stage to
45db??

Thanks in advance,

Regards,
Partha!

__________________________________________________
Do you Yahoo!?
Yahoo! Tax Center - forms, calculators, tips, more
http://taxes.yahoo.com/
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: