[SI-LIST] Re: Decoupling capacitors

  • From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 26 Jun 2002 12:32:22 -0700

Larry,

Thanks for your additional comments.  I understand what you say about
components that can be had today and, more so than that, not adding to the
bottom line.

I've got to tell you that the variables involved in this issue of PDS design
have caught me by surprise.  Every article I read has me going in a
different direction.  I don't know which way to move to get out of my own
way!

To this, add application notes (like one from a very prominent memory
manufacturer) that are flat wrong --the one I'm talking about calls out for
the same value and quantity of capacitors whether you enter 1sec or 1ps for
rise-time into their equations!

Then there's the Johnson "High Speed Digital Design..." approach that seems
to produce answers with such large quantities of caps that I'm not sure
where you'd put them.  One example produced an array of some 76 ceramic
capacitors for ONE dynamic ram chip. One.  Where do you put them?  And,
better than that, I've never seen a memory board with that many caps per
chip.  So, where does reality intersect with number-crunching?

In other cases (Xilinx) there are conflicting app notes and articles, where,
in one case, you are told to use an array of ceramic chip caps right under
the package and tantalums (greater than 47uF) within a couple cm and, in the
other case, use a series of several values distrbuted from the package out.

The more you read the more you could think that the problem would be
insurmountable if it wasn't that there are tens of thousands of
high-performance designs out there, from PC's on up.  Where are the limits
between reality and seeking perfection?  Does one really need high-end
simulation tools in order to prevent disaster?  How does a guy (me?) decide
on a PDS scheme for a simple little board with a couple of Xilinx FPGA's
running in the 75MHz to 165MHz range and a few other chips in the same
range?

Is this going to be an iterative process no matter how hard one tries?  In
other words: count on your first board layout not working and optimize from
there?

One question I have regarding the use of series resistors to improve the
performance of small-valued caps is:  Barring the possibility of using
specialized caps or PCB's, would it be too far fetched to simply add a
physical series resistor to decoupling caps?  If both the cap and the
resistor are downsized as far as possible, say 0201, would the added
inductance of this approach be countered by lower package inductance?  I can
see doing this under an FPGA, for example, where, instead of connecting the
caps directly to the central ground area you'd add a number of small series
resistors.

I'm still reading through papers (about 15 of them), including yours.  I've
got to arrive at a decision soon.  Part of that decision might be whether or
not I shuold seek the help of a PDS/SI expert in order to avoid pitfalls
that require more experience with high-performance PDS rather than raw
equation crunching.

I do appreciate your input as well as all others' who've posted to this
thread.

Thanks,


===============================
 Martin Euredjian
  eCinema Systems, Inc.
===============================


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