[SI-LIST] Re: Decoupling capacitors

Martin and all - there have been some good comments on this thread.
I'll try to add a few more...

It is not necessary to make the impedance vs frequency of the power
distribution system (PDS) absolutely flat.  A few ripples will not hurt
you but you want to try to keep those ripples below the target
impedance.  By definition, if you meet the target impedance you will
have voltage ripple on the PDS that is the same percentage of the power
supply voltage that you used in the Ztarget calculation  and occurs
when the load draws the maximum current transients.  Dips in impedance
do not hurt you but peaks do.

        Ztarget = Vdd x tolerance / transient_current

The reason for having all the capacitor values, which leads to all the
impedance notches, is to be able to use the capacitors that are
commonly available in the industry today.  Istvan Novak (my Sun
colleague) and some others have proposed using controlled ESR
capacitors, either by resistance in the capacitor itself or in the
mounting structure of on the PCB.  This is a good technical solution
and produces a flat impedance vs frequency curve with a single part
number component -- very desirable.  

The biggest problem with this technique is that controlled ESR
capacitors are not available in the industry today.  They probably
could be developed on some kind of a time and development-cost
schedule.  We would need a menu of ESR values to satisfy the needs of
products with unique Ztarget and maximum frequency requirements.
Personally, I work in a components group where the big rule is "Thou
shalt not add any cost to the product"  unless you have a really good
reason.  While controlled ESR techniques are attractive, PCB and
internal-capacitor techniques are bound to add cost, not to mention
inventory and supply issues for the several different ESR values. 

This brings us back to where we started, trying to use the capacitors
that are readily available today.  That means using several different
capacitor values and having many frequency notches along the way in
order to achieve a relatively flat impedance vs frequency.  Perhaps
this solution is not optimum, but it is here today with a well
understood cost.

The second part of your question...  You have to be careful in using
your proposed menu of 16 tantalums in parallel with 73 x 0.01uF ceramic
caps.  Istvan has already mentioned the capacitance of the power planes
resonating with the parallel inductance of the capacitors.  This will
form an impedance peak that may be an EMI concern if it gets stimulated
by a clock or harmonic.  It may also be an SI concern for high
frequency communication chips.

Another concern is the chip capacitance mounted on the power planes in
some kind of an electronic package.  For a typical micro processor
chip, this is likely to be 300 nF.  The chip capacitance will create a
-20 dB/decade slope on the impedance vs frequency graph that may
intersect with the +20 dB/decade slope of the parallel
capacitor-inductors.  The PDS is intentionally designed with low
resistance so this is likely to be a very high Q resonant peak.  When
the chip circuits look out through the package, they will see this
resonant peak.  It is likely to cause trouble for the chip when some
customer code accidentally stimulates that resonance.

Even if we had perfect, zero impedance power planes on our PCB up to 1
GHz, chip/package resonance (where the chip capacitance resonates with
the package inductance) is a major problem.  If the PCB presents an
inductive slope at the chip/package resonant frequency, the problem
only becomes worse.  The best thing the PCB can do is present a
resistive impedance to the processor package at the chip/package
resonant frequency.  A resistive PCB adds damping to the system and
reduces chip/package resonance.  An inductive PCB adds reactance to
the system and increases chip/package resonance.  This is the major
reason for keeping the impedance flat on the PCB rather than allowing
reactive slopes to occur.

regards,
Larry Smith
Sun Microsystems

> Delivered-To: si-list@xxxxxxxxxxxxx
> From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] Re: Decoupling capacitors
> Date: Sun, 23 Jun 2002 15:57:43 -0700
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> 
> Abe Riazi wrote:
> ...
> > ... in some other cases it is preferable to use multiple values of
> > capacitance (with low ESL) to satisfy a desired flat low PDS impedance
> over
> > a specified/broad frequency bandwidth.
> ...
> 
> I've modeled (and, yes, models can't always be trusted) alternatives with
> hundreds of caps of different values and packages covering a range from low
> frequency to high frequencies and in various combinations.  My conclusion
> from this experience is that you cannot achieve a "flat" impedance over a
> frequency range (probably obvious) and that the "shotgun" approach of
> peppering the board with a wide range of values may not produce a usable
> performance change.  This is due to the interplay of the RLC components in
> any capacitor producing the familiar V shaped impedance curve.  You can get
> an impedance curve that has all these nicely spaced notches, but flat it
> will not be.
> 
> And then the question is?  does it really need to be flat?  And super low?
> I mean --oversimplifying-- once the PDS can can deliver the required current
> within a given frequency range, why go any lower?  Why introduce all these
> notches with dozens of capacitor values?
> 
> The PDS I now have on paper consists of 16x 150uF, 0.1ohm tantalums and 73x
> 0.01uF, 0402 chip caps.  On paper, and in theory, this PDS can deliver an
> impedance of less-than 0.01ohms from about 20KHz to about 200MHz and
> less-than 0.05ohms from 200MHz to about 1GHz.  And, all else being adequate,
> this would mean a theoretical current delivery capability of at least 60A at
> 3.3V from 20KHz to 1GHz ... with two capacitor values!
> 
> Of course, I know that this is far from reality.  PCB trace, layout, package
> effects, etc. getting in the way of perfection.  Mother Nature always wins.
> However, it does beg the question:  What do you really need in order to
> achieve the required frequency-current budget?  My gut feeling is that a
> couple of well-chosen capacitor values along with good layout/placement
> should do for all but the most esoteric applications.
> 
> 
> ===============================
>  Martin Euredjian
>   eCinema Systems, Inc.
> ===============================
> 
> 
> 
> 
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