[SI-LIST] Re: Decoupling capacitors

Martin, Abe,

Please note that the ESR = X1 = -X2 condition at the antiresonant point
ensures flat impedance response only if Q of both parts is very low.
Otherwise the impedance profile will have ripples even if that condition is
met.  However, as it was pointed out correctly, the ripple itself does not
matter as long as the peaks are still below the spec, or if there is no
noise contents exciting the peaks.

Martin,

The numerical example you mention, with 15x150uF 0.1ohm tantalums and
73x0.01uF ceramics will yield a flat (lumped) impedance response with
<0.01ohm impedance up to 200MHz, only if the tantalums had <0.7nH inductance
each, something that is close to impossible to achieve.  The tantalum
capacitors of this size most probably would have an inductance around 3-5nH
each.  With 4nH assumed, the spreadsheet predicts a 46milliohms peak at
11.5MHz.  You could eliminate the extra peak and still use 150uF 0.1ohm 4nH
tantalum caps if instead of 0.01uF capacitance you choose 0.1uF for the
ceramic part.  If you do one or the other, the only remaining peaks may come
from capacitor-to-plane resonances or from plane modal resonances.  With
regular low-ESR 0.01uF or 0.1uF ceramic capacitors you may end up having
both.

Note also the interesting scenario in the above (lumped) example where one
low-Q capacitor bank (150uF 0.1ohm) is connected to one low-ESR (0.1uF)
capacitor bank.  Relatively flat impedance response can be achieved as long
as there is only one low-ESR element involved.  In other words a deep
minimum over a relatively flat impedance response will create very minimal
peaking.  Adding one more deep notch, however, will immediately create an
antiresonance peak, which in the above example may (bot not necessarily
will) come from the impedance minimum (or minima) of connecting planes.

Regards
Istvan Novak
SUN Microsystems

----- Original Message -----
From: "Abe Riazi" <ARIAZI@xxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, June 25, 2002 1:18 AM
Subject: [SI-LIST] Re: Decoupling capacitors


>
> Hi Martin:
>
> Please find inserted my reply to your comments.
>
> Martin Euredjian Wrote:
> >
> > Abe Riazi wrote:
> > ...
> > > ... in some other cases it is preferable to use multiple values of
> > > capacitance (with low ESL) to satisfy a desired flat low PDS impedance
> > over
> > > a specified/broad frequency bandwidth.
> > ...
> >
> > I've modeled (and, yes, models can't always be trusted) alternatives
with
> > hundreds of caps of different values and packages covering a range from
> low
> > frequency to high frequencies and in various combinations.  My
conclusion
> > from this experience is that you cannot achieve a "flat" impedance over
a
> > frequency range (probably obvious) and that the "shotgun" approach of
> > peppering the board with a wide range of values may not produce a usable
> > performance change.  This is due to the interplay of the RLC components
in
> > any capacitor producing the familiar V shaped impedance curve.  You can
> get
> > an impedance curve that has all these nicely spaced notches, but flat it
> > will not be.
> >
> Actually, it is possible to obtain an impedance curve which is relatively
> flat,
> but it is influenced by several parameters such as frequency, ESR, number
> and values of capacitors.
> In reference 1, it is shown that for a two capacitor configuration the
> mathematical
> condition for obtaining an approximately flat impedance reponse curve is
> given by:
>
> ESR = X1 = -X2       (at anti-resonant points)
>
> Where, X1 and X2 are the imaginary parts of each capacitor's impedance.
>
> > And then the question is?  does it really need to be flat?  And super
low?
> > I mean --oversimplifying-- once the PDS can can deliver the required
> current
> > within a given frequency range, why go any lower?  Why introduce all
these
> > notches with dozens of capacitor values?
> >
> Minimizing noise/radiation and meeting timing and speed requirements are
> among the reasons why it is desirabable for a power disctribution to
possess
> a (nearly) flat low impedance over a wide frequency range.
> Please see references 2 and 3.
>
> > The PDS I now have on paper consists of 16x 150uF, 0.1ohm tantalums and
> 73x
> > 0.01uF, 0402 chip caps.  On paper, and in theory, this PDS can deliver
an
> > impedance of less-than 0.01ohms from about 20KHz to about 200MHz and
> > less-than 0.05ohms from 200MHz to about 1GHz.  And, all else being
> adequate,
> > this would mean a theoretical current delivery capability of at least
60A
> at
> > 3.3V from 20KHz to 1GHz ... with two capacitor values!
> >
> How did you determine that above PDS deleivers impedance of less than
> 0.05 from 200 MHZ to 1Ghz?
> Did you anlyze the resonat freqeuncies, poles and zeros?
> Did you simulate?
>
> > Of course, I know that this is far from reality.  PCB trace, layout,
> package
> > effects, etc. getting in the way of perfection.  Mother Nature always
> wins.
> > However, it does beg the question:  What do you really need in order to
> > achieve the required frequency-current budget?  My gut feeling is that a
> > couple of well-chosen capacitor values along with good layout/placement
> > should do for all but the most esoteric applications.
> >
> It is difficult to draw accurate conclusions regarding how many caps are
> required for
> a PDS without analyzing the  poles and zeros of the system. Designing a
high
> performance PDS usually requires simulation to determine what distribution
> of
> capacitance, ESL and ESR are required for optimum decoupling meeting the
> design specifications.
>
> Best Regards,
>
> Abe Riazi
> ServerWorks
>
> References:
>
> 1. Douglas G. Brooks, "ESR and Bypass Capacitor Self Resonant
> Behavior How to Select Bypass Caps"
>
> 2. Larry D. Smith, "Decoupling Capacitor Calculations for CMOS Circuits"
>
> 3. Valeri St. Cyr, Istvan Novak, Nick Biunno, Jim Howard,"
> ARIES: Uisng Annular-Ring Embeded Resistors to Set Capcitor ESR
> in Power Distribution Networks"
>
> Note: Soft copies of above papers are available
>
>
>
>
>
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