[SI-LIST] Re: Decoupling capacitors

Martin,

You are right, the term controlled-ESR capacitor may not be defined in any
of the papers to which I sent you the pointers earlier today.  This is an
emerging definition, referring to capacitors, which have the ESR specified
on their data sheet.  Controlled ESR is the first step; it will allow
designers to estimate the worst-case behavior of a power distribution
network.  The next step is to provide bypass capacitors where you can select
from a range of (controlled) ESR values: this is what I referred to in the
earlier message as BYPASS RESISTORS, as the resistance becomes the primary
parameter, and the capacitance value does not matter much, we just want the
highest capacitance in a given package.

Regards

Istvan Novak
SUN Microsystems


----- Original Message -----
From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
To: "Istvan Novak" <istvan.novak@xxxxxxxxxxxxxxxx>
Sent: Monday, June 24, 2002 4:52 PM
Subject: RE: [SI-LIST] Re: Decoupling capacitors


> Istvan,
>
> Thank you for the pointers.  I'll study the various papers carefully.
>
> Can you tell me what the difference is between "low ESR" --like the
> Panasonic LETCAP line-- and "controlled ESR" capacitors?
>
> Thanks again,
>
> ===============================
>  Martin Euredjian
>   eCinema Systems, Inc.
>        voice: 661-305-9320
>        fax:   661-775-4876
>   martin@xxxxxxxxxxxxxx
>   www.ecinemasys.com
> ===============================
>
>
>
>
>
> -----Original Message-----
> From: Istvan Novak [mailto:istvan.novak@xxxxxxxxxxxxxxxx]
> Sent: Monday, June 24, 2002 5:55 AM
> To: martin@xxxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: Decoupling capacitors
>
>
> Martin,
>
> Here are some pointers for your convenience:
>
> 1., The paper describing results with the design where 250 plus bypass
> capacitors were replaced with 50 pieces of controlled-ESR capacitors was
> presented at EPEP2001: "ARIES: Using Annular-Ring Embedded Resistors to
Set
> Capacitor ESR in Power Distribution Networks".  The manuscript and slides
> are available at http://home.att.net/~istvan.novak/papers.html  A more
> detailed follow up paper is scheduled to appear in the IEEE Transaction
> CPMT, August 2002.
> 2., Controlled-ESR capacitors are coming from AVX.  Last year AVX
presented
> their first results in the paper: Korony, et. al., "Controlling Capacitor
> Parasitics for High Frequency Decoupling" Proceedings of IMAPS2001, 2001
> October 9-11, 2001, Baltimore, Maryland
> 3., Tools for checking various possible combinations of bypass capacitor
> parameters: for detailed analysis at high frequencies (when horizontal
plane
> interconnections do matter) SPICE or similar tools should be used.  For
> first-cut analysis, lumped-model calculations are useful and adequate.
> Simple 'calculators' are available from UltraCAD at www.ultracad.com, or
you
> can download the Excel spreadsheet from
> http://home.att.net/~istvan.novak/tools.html  This latter spreadsheet
allows
> you to specify +- tolerances for the Cs, ESRs and ESLs of three
independent
> capacitor banks, and if you enable macros, you can ask the spreadsheet to
> calculate the minimum and maximum impedance curves under all possible
> tolerance combinations.
> 4., Further details of two-port VNA measurements are posted at
> http://home.att.net/~istvan.novak/papers.html
> - DesignCon 1999: Probes and Setup for Measuring Power-Plane Impedances
with
> Vector-Network Analyzer
> - DesignCon 2000: Measuring Milliohms and Picohenrys in Power Distribution
> Networks
> - also the files ectc_2001, ectc_2002_cap and ectc_2002_pds at
> http://groups.yahoo.com/group/si-list/files
>
> As it was properly mentioned by Robert, controlled-ESR capacitors are not
> common today: the EPEP paper describes a solution where no controlled-ESR
> capacitor is required: the proper ESR is set by embedded printed
thick-film
> resistors, so any low-ESR high-Q ceramic capacitor can go with it.  Some
> forms of capacitors are suitable as they are for the low-Q design
> methodology: tantalum capacitors and aluminium electrolytic capacitors
have
> high (but still not tightly specified) ESR.  Conventional tantalum bricks
> and aluminium cans tend to have somewhat high inductance, but in some
design
> scenarios it may not matter.
>
> Regarding controlled-ESR capacitors:
> - the embedded thick-film implementation has been tested and found to be
> ready for volume applications.
> - ceramic capacitors with controlled-ESR may be available in the near
> future.  As it was mentioned on this list earlier with respect to
> simulation-tool features, the more people ask for, the sooner it arrives.
>
> regards
> Istvan Novak
> SUN Microsystems
>
>
> ----- Original Message -----
> From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Sent: Friday, June 21, 2002 2:51 PM
> Subject: [SI-LIST] Re: Decoupling capacitors
>
>
> >
> > I just signed-up to this list read through most of this thread in the
> > archives.  I was intrigued by Istan Novak's post, and the approach he
> > suggests:
> >
> > "One of the published examples replaced about 250 pieces of
different-size
> > different-value bypass capacitors with 50 pieces of controlled-ESR 2.2uF
> > capacitors on a CPU card. Apart of two bulks, there was only this single
> > value of bypass capacitor on the board, achieving the minimum number of
> > bypass capacitors, and at the same time effectively suppressing
> > capacitor-to-capacitor, capacitor-to-plane, and modal plane resonances."
> > ....
> > "Measured data supporting the claims/statements (except the last item)
on
> > the above list, including more details about implementations, have
already
> > been published and is available on line."
> >
> > Can someone (Istan?) post a link to further information on this
approach?
> >
> > I am trying to decide on an approach to take on a simple design I'm
> working
> > on; just a couple of XC2V1000's, some 133MHz SDRAM and half a dozen
other
> > devices.  HD video processing.  Data rates from 74MHz to 165MHz, if you
> > ignore GHz in/out section.
> >
> > What I've read so far from other sources has me a bit confused as to
which
> > approach might be the safest.  One camp goes for a lot of caps and a
> > half-dozen or more values.  Some of my own -basic- simulations tell me
> that
> > a bunch of 0402 (low ESL, ~0.6nH?) 0.01uF's right on the power pins and
a
> > generous number of 150uF, 0.1ohm (~3.4nH?) tantalums distributed
> throughout
> > the board might do just as well.
> >
> > Frankly, I'm having trouble deciding which way to go.  And, now, of
> course,
> > I read that a valid solution may exist --if I understand it correctly--
> > without the use of hundreds of small caps.  This, of course, is very
> > attractive from many perspectives and I'd like to learn more about it.
> >
> > Finally, a question:
> > How do large valued (>1uF) multilayer chip caps compare to tantalums for
> > high-speed and bulk decoupling?  Panasonic has values all the way up to
> > about 100uF but very little performance data (ESR, ESL, SRF?)
> >
> >
> > Thanks,
> >
> >  Martin Euredjian
> >  eCinema Systems, Inc.
> >
> >
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> >
> >
>
>
>

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