[SI-LIST] Re: Decoupling capacitors

Martin Euredjian Wrote:

> What I've read so far from other sources has me a bit confused as to which
> approach might be the safest.  One camp goes for a lot of caps and a
> half-dozen or more values.  Some of my own -basic- simulations tell me
that
> a bunch of 0402 (low ESL, ~0.6nH?) 0.01uF's right on the power pins and a
> generous number of 150uF, 0.1ohm (~3.4nH?) tantalums distributed
throughout
> the board might do just as well.
>

Hi  Martin:

I have also noted that some high speed PCBs utilize only a single
capacitance with same dielectric and package type (Example: 0.1uF, X7R,
0603 ceramic chips) for all required high frequency decoupling capacitors,
 as this offers simplicity and economy.

However, in some other cases it is preferable to use multiple values of
capacitance (with low ESL) to satisfy a desired flat low PDS impedance over
a specified/broad frequency bandwidth. In the latter approach it is usually
necessary to simulate and analyze the system resonant (series and parallel)
frequencies (and Q factors) in order to ascertain how many ceramic
capacitors
and within what value ranges/distribution (for capacitance, ESR and ESL) can
yield optimum high frequency decoupling.

Additionally (as you have mentioned), certain number of bulk  large tantalum
or electrolytic caps are also needed for low frequency decoupling.

Best Regards,

Abe Riazi
ServerWorks







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