[SI-LIST] Re: Decoupling capacitors
- From: "Robert Sefton" <rsefton@xxxxxxxxxxxxx>
- To: <martin@xxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 21 Jun 2002 12:08:47 -0700
Martin -
I believe this approach depends on "controlled-ESR" caps, which are not
available yet (vs. low-ESR caps which are available but can cause problems
in bypass apps).
Robert
----- Original Message -----
From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Friday, June 21, 2002 11:51 AM
Subject: [SI-LIST] Re: Decoupling capacitors
>
> I just signed-up to this list read through most of this thread in the
> archives. I was intrigued by Istan Novak's post, and the approach he
> suggests:
>
> "One of the published examples replaced about 250 pieces of different-size
> different-value bypass capacitors with 50 pieces of controlled-ESR 2.2uF
> capacitors on a CPU card. Apart of two bulks, there was only this single
> value of bypass capacitor on the board, achieving the minimum number of
> bypass capacitors, and at the same time effectively suppressing
> capacitor-to-capacitor, capacitor-to-plane, and modal plane resonances."
> ....
> "Measured data supporting the claims/statements (except the last item) on
> the above list, including more details about implementations, have already
> been published and is available on line."
>
> Can someone (Istan?) post a link to further information on this approach?
>
> I am trying to decide on an approach to take on a simple design I'm
working
> on; just a couple of XC2V1000's, some 133MHz SDRAM and half a dozen other
> devices. HD video processing. Data rates from 74MHz to 165MHz, if you
> ignore GHz in/out section.
>
> What I've read so far from other sources has me a bit confused as to which
> approach might be the safest. One camp goes for a lot of caps and a
> half-dozen or more values. Some of my own -basic- simulations tell me
that
> a bunch of 0402 (low ESL, ~0.6nH?) 0.01uF's right on the power pins and a
> generous number of 150uF, 0.1ohm (~3.4nH?) tantalums distributed
throughout
> the board might do just as well.
>
> Frankly, I'm having trouble deciding which way to go. And, now, of
course,
> I read that a valid solution may exist --if I understand it correctly--
> without the use of hundreds of small caps. This, of course, is very
> attractive from many perspectives and I'd like to learn more about it.
>
> Finally, a question:
> How do large valued (>1uF) multilayer chip caps compare to tantalums for
> high-speed and bulk decoupling? Panasonic has values all the way up to
> about 100uF but very little performance data (ESR, ESL, SRF?)
>
>
> Thanks,
>
> Martin Euredjian
> eCinema Systems, Inc.
>
>
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>
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- References:
- [SI-LIST] Re: Decoupling capacitors
- From: Martin Euredjian
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- [SI-LIST] Re: Decoupling capacitors
- From: Martin Euredjian