[SI-LIST] Re: Decoupling capacitors
- From: Paul Levin <levinpa@xxxxxxxxxxxxx>
- To: degers@xxxxxxxxxxxxxxxxxxxx
- Date: Fri, 07 Jun 2002 10:36:40 -0700
Dear All,
Perhaps this is too simplistic approach, but what about connecting two pieces of
coax to the power and ground planes such that they are "fairly close" together.
If one were to measure S21, one should get nearly 0 dB without any power plane
and decoupling. Were the impedance to be 1 ohm at some frequency, I would
expect -40 dB for S21. Given the sensitivity of a VNA, I would think you could
measure down to 0.01 ohm or less.
Any thoughts?
Paul
--
Paul A. Levin
Senior Principal Engineer
Xyratex, Manhattan Beach
(310) 372-7352 - home & office
(310) 291-8199 - cell
______________________________
"Michael J. Degerstrom" wrote:
> Larry,
>
> Your comments below bring up an interesting point. While I've always thought
> it would be good to measure the PDS, I've never have attempted it as I didn't
> know how to provide an effective launch. Lets make some assumptions to
> clarify things. First lets say we are trying only to measure the PDS from
> the pcb and so we will not include the package PDS for now. Next assume that
> the active chip has an effective impedance of 2 ohms. Using your 20X rule
> then your PDS should be 2/20 = 0.1 ohms. How can you measure this impedance
> with a VNA having 50 ohm ports with commercial probes that generally have
> coplanar launches? Furthermore, the PDS achieves its low impedance, in part,
> because it utilizes parallel structures. For example, there are many power
> and ground pads from the package to the pcb. The VNA can only measure
> between one power and two ground pads using a GSG coplanar probe in this case.
>
> One approach is to design a special test case where most of the PDS is
> removed. For example lets say your package is a quad-flat package and has 50
> power and 50 ground pins spread uniformly around the package. One could
> design a test board with most of plane removed forming a wedge whose "point"
> connects up to one package power pin and one package ground pin and the rest
> of the wedge reaches out to the perimeter of the board. Then simply do a one
> port impedance measurement and divide the resulting impedance by a factor of
> 50 to obtain the PDS impedance. The problem with this approach is that your
> various decoupling capacitors will probably be much fewer than 50 each and so
> if one of these capacitors is tied into the wedge it provides more decoupling
> than what is realistic. Also, I deliberately chose a quad-flat package as
> the pins are on the package periphery. How does one accommodate a BGA where
> the power/ground pins may be stacked several rows deep?
>
> So if one does not make accommodations for the fact that the PDS is a
> distributed structure then I guess you will still be able to obtain your PDS
> impedance over very low frequencies but above some cutoff frequency the
> measurement is no longer valid.
>
> Mike
>
> On Thursday 06 June 2002 02:05 pm, Larry Smith wrote:
> > Jim - We usually make measurements on passive boards which are not
> > connected to a power source. All components (uP, SRams, etc) are
> > usually on the board but are not usually a big factor in the
> > measurement. You want the PDS to be about 20 times stronger than the
> > active chips. This is a natural outcome of using 5% tolerance in the
> > target impedance calculation and PDS design.
> >
> > It is certainly possible to make measurements on an active board, fully
> > powered up and functioning. Just make sure your VNA will tolerate the
> > DC bias.
> >
> > We sometimes apply DC bias to the DUT by using the terminals on the
> > back of the VNA. Our VNA will tolerate up to 30 amps DC but we have
> > never pushed it that far.
> >
> > regards,
> > Larry
> >
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