[SI-LIST] Decoupling Cap. Strategies.

        Hi All Gurus,

        What are the different decoupling capacitor placement and routing
strategies for high speed boards...?
        If you specifically make a band of high frequencies like
        1. up to 150 MHz.
        2. 150 to 500 MHZ
        3. 500 MHz and above.

        I can understand that for 50MHz and above designs every thing will be 
cross
calculated and possibly simulated before finalizing.

        I just want to ask that for any design the strategy of putting a via to 
a
power plan directly on the Capacitor Pad will work fine...? or there has        
to
be some calculation and evaluation of the decoupling strategy for every
design.

        Please if anybody can suggest any guidelines or documents it will be 
very
helpful.

        I am getting many things on the net also and getting guideline documents
from the chip manufacturers as well but a good discussion will  always help
me to finalize my strategic goal.

        Thanks & Regards,
        Kedar


http://www.patni.com
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