[SI-LIST] Re: DecapPlacement
- From: "Jim Whitehead" <jim.whitehead@xxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 15 Mar 2007 19:05:21 -0400
A-Men! My biggest problem (usually) has been how to find real-estate
for all of those caps on BOTH sides of the board. The stackup would
help here, too. In general, the highest/fastest A/C current source
planes should be placed closer to the side of the board (top or bottom)
for the consuming IC in question; board thickness and via aspect ratio
come into play here and make this more or less effective. If you keep
in mind the name of the game is to minimize the apparent mounting
inductance and spreading inductance from the source (plane, decoupling
caps, device package); intuition breeds concept, calculation/simulation
breeds success.
If you don't have it already, there is a very good book out there that
explains this in great detail. It also shows how to use common tools
like Excel to get started in the design of your power sub system. Be
cognizant of parallel resonance effects due to any internal board
capacitance (IBC) layers (and caps neighboring in freq) and you'll be
sure to get it "Right The First Time"!
Link to book =3D http://speedingedge.com/rtft_book.htm
(If it is inappropriate to "plug a book" in this forum, I apologize.
But trust me on this one; it is certainly worth the read)
Cheers,
Jim
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Thursday, March 15, 2007 10:38 AM
To: Jack Olson; sreekanthn@xxxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DecapPlacement
If your planes are continuous, there is little benefit to placing
capacitors on one side of a PCB vs. the other. All that might be
achieved
in a slightly lower mounting inductane based on how deep into the PCB
the
vias have to reach to connect to the planes. However, this delta L only
moves the self resonant frequency of the capacitors a little higher or
lower. In a normal PCB, this is not enough of a gain to warrant
penalizing
assembly by placing capacitors on the bottom the PCB, if so doing
results
if double sided assembly.=20
There are many papers published that support this.
Lee Ritchey
Speeding Edge
> [Original Message]
> From: Jack Olson <pcbjack@xxxxxxxxx>
> To: <sreekanthn@xxxxxxxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 3/14/2007 8:07:08 PM
> Subject: [SI-LIST] Re: DecapPlacement
>
> We put nearly ALL of our decoupling on the back.
> Remember that even if the components are side by side,
> the vias still have to get to the planes and back, making it
> often the same electrical distance away. In other situations
> the distance is even closer from the back because the
> decoupling part can be placed directly under the power
> pad, rather than being placed some distance away for
> package size clearances.
> best wishes,
> Jack
>
>
> On 3/12/07, Sreekanth N nampoothiri <sreekanthn@xxxxxxxxxxxxxxx>
wrote:
> >
> > Dear Group,
> >
> > How much ll be the bad effect if we place a decap
in
> > the
> > opposite side of the mother IC,if the design is in 200+ MHz range?
> > Do we have any rule of thumb regarding the decap
> > handling?
> >
> >
> > Best Regards,
> > Sreekanth N Nampoothiri
> >
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