[SI-LIST] Re: Data Bus termination

Abe,
You are correct that for a bidirectional bus, series terminations may be 
required at the both ends of the bus.  Depending on the driver impedance, 
one may be able to manage with only one termination.  I was simulating the 
interface between our memory controller ASIC and a single DDR2 DRAM.  The 
memory interface impedance can be programmed to 20 ohms or 40 ohms.  I 
found out that with 40 ohm impedance driver, I could manage with only one 
termination at the DRAM end.  However, with 20 ohm driver, I needed 
terminations at both ends.  I tried moving the single termination around 
(at either end as well as in the middle), but the overshoot was always 
excessive. 

Regards, Ravinder
Server PCB Development
Hitachi Global Storage Technologies

Email: Ravinder.Ajmani@xxxxxxxxxxxxxx



"ariazi" <ariazi@xxxxxxxxxxxxxxx> 
Sent by: si-list-bounce@xxxxxxxxxxxxx
06/29/2005 11:27 AM
Please respond to
ariazi@xxxxxxxxxxxxxxx


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Subject
[SI-LIST] Re: Data Bus termination







Dear Mahesh,

Series termination is the most common selection for a point-to-point
topology.

When the bus is unidirectional, the ideal placement for the source
terminator is close to
the driver. For series termination of a bidirectional bus two resistors 
may
be required
(one near each agent) or just a single resistor some where in the middle 
of
the line.

There exist rules of thumb and mathematical formulas for determining the
effective 
locations and values for series terminators. However, the need for and the
optimum 
termination solution is usually ascertained with aid of simulation. 
 
Best Regards,

Abe Riazi
ServerWorks

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] 
On
Behalf Of mahesh.linge@xxxxxxxxx
Sent: Wednesday, June 29, 2005 12:32 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Data Bus termination



Hi,
I have Processor Flash and SDRAM on my board.My data bus is running at 125
MHz.I would like to know placement of the series termination resistors on
the data bus as it will be a bisectional.

Thanks in advance.

Regards,
Mahesh


 


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