[SI-LIST] Re: DQS vs DDR CLOCK TIMING
- From: steve weir <weirsp@xxxxxxxxxx>
- To: sidney16481@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 23 Feb 2004 05:30:04 -0800
Sidney, DDR is source synchronous timed with the burden loaded heavily on
the controller. It is up to the controller / system implementation to skew
DQS properly for the transfer direction. DQS is relative to data at each
source. DQS to clock timing allows DQS sampled data to pass into a CK
clock domain in a controlled manner.
If you are having trouble interpreting the JEDEC documents, there are a
number of app notes around. But, if the real issue is that this is your
first DDR design, there are design houses and consultants who can help you
with either canned solutions, or customization for your needs. If you are
trying to operate at DDR333 or above and you are new to this, you would be
wise to get some help.
Steve.
At 04:02 AM 2/23/2004 -0800, Sidney S wrote:
>Hi,
>
>I am doing timing analysis for the DDR SDRAM interface. I would like to
>know how to do timing analysis for strobe vs clock since these signals
>also has to be matched.
> For instance, the DQS setup and hold time is mentioned in
>the JEDEC spec for the falling edge, but how do I consider it for timing
>when the clock to SDRAM is from the chipset.
>Should I consider two instances one for the falling edge (read and write)
>and the other for rising edge (read and write operation)?
>How should I consider the parameters Tdqss and Tdqsck?
>
> Please help....
>Thanks,
>Sidney.
>
>
>
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