[SI-LIST] DQS vs DDR CLOCK TIMING

Hi,
 
I am doing timing analysis for the DDR SDRAM interface.  I would like to know 
how to do timing analysis for  strobe vs clock since these signals also has to 
be matched.
 For instance, the  DQS setup and hold time is mentioned in 
the JEDEC spec for the falling edge, but how do I consider it for timing when 
the clock to SDRAM is from the chipset. 
Should I consider two instances one for the falling edge (read and write) and 
the other for rising edge (read and write operation)?
How should I consider the parameters Tdqss and Tdqsck?
 
 Please help....
Thanks,
Sidney.



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