[SI-LIST] Re: DDR-400 T-topology and simulation questions

Hi Chuck,

It seems that you didn't balance the address signals correctly.
The length of the traces after the split to each DDR device must be matched
exactly (same length). So each DDR device in the chain sees the signal at
the same time.

Best Regards,
Hans Klos

Senior SI consultant
Sintecs BV
The Netherlands
http://www.sintecs.nl


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of CR
Sent: maandag 25 juni 2007 6:41
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR-400 T-topology and simulation questions

Hi,

I've read topics from this list before and they have been invaluable.  I
have some questions on an embedded DDR-I 400 MHz design I'm working on, I'd
really appreciate some advice here.  I've done slower speed DDR, always
single-device, point-to-point, not like this though.

I also apologize in advance if this message seems too long, I'm trying to
provide right background info.

* Memory controller is 64-bit wide
* I'm using four DDR-400 x16, 2.6V , all parts soldered down, no sockets
* Addr/cmd is shared among all four devices
* Data byte lanes are completely point-to-point; using reduced drive
strength on DDR DQ/DQM/DQS
* ASIC supports Class I & Class II drive-strength on all I/Os

Current topology:

Data:
* Series termination on byte-lanes in middle of route, no use of Vtt
* Traces ~1.5 - 1.7" long
* 60 ohms target impedance for tlines

Addr/cmd:

* Using T for addr/cmd (no choice)
* Series ~22 ohm from driver, 62 ohms to Vtt at split-point; suggested
topology by memory vendors

* ~60 ohms target impedance for tlines, routed against VCC image plane
(either on layer below or layer above VCC plane).

* Due to ball-out of ASIC, addr/cmd is routed horizontally as a bus from
ASIC, then addr/cmd signals from DDRs are routed vertically on a different
layer and intersect horizontal routes with vias.

* ~500 mil from ASIC BGA to series resistor.  Max ~500 mil from resistor to
T spilt-point (via)

* Worst mismatch in T for all addr/cmd: Stub from split-point via to closest
DDR typically ~50 mil, then ~700 mil to next DDR.  On other side of via 1"
to one DDR then 700 mil to the last DDR.

Problems:

Ball-out of ASIC and mechanical placement has forced addr/cmd to be routed
as a group horizontally and to be T'd vertically up/down to DDRs.  This
results in unbalanced T-structure for majority of addr/cmd.

Simulations show even with 62 ohms to VTT (1.3V) at split-point (T) there is
a lot of ringing, especially at middle DDR devices.  

Putting Vtt at both ends improves end devices some but middle devices still
look horrible (overshoot and ringing).  Seems mis-match in T lengths is
causing majority issues.

My questions:

1.  How have some of you dealt with the T of your addr/cmd?  Did you balance
every route?  

Seems like placing via's equdistant for ALL branches of T would add routing
length from the horizontal path to split-point via (i.e. U shaped traces).

2.  I had more positive results with a 10 ohm series to the T's and then 22
ohms off each T to the branches.

The source 10 ohm ends up limiting maximum overshoot at the ends so I think
it's needed (at least at fast drive strength).

Any comments on this topology? Any thoughts on improving it?

3.  Any thoughts on adding delay to CLK so it aligns more with center of the
addr/cmd signal?

I would of course need to take into consideration worst case skew (min/max
lengths of addr).

4.  What are some of the simulation techniques you use to judge SI for DDR?

I've been using HyperLynx and set a questionable line (addr in this case) to
toggle at max clock rate (200 MHz) since one can have a run of eight
outstanding posts to DDR, I figure that will give a good indication of
ringing after a few cycles.

I use observation at IC die instead of pin.

I also use the eye feature and observe opening of Vih/Vil AC and DC after a
long length of runs.

Will using an eye like this give me an overly pessimistic result?  Addr/cmd
even at 1T doesn't continue indefinitely (I think).

For timing measurements I use HL's slew rate and rise/fall time measurements
using Vih(ac) and Vil(ac) thresholds.

I sweep this across slow/normal/fast IBIS drive levels but have less faith
in the "slow" since power supply is well controlled.  A mistake on my part?

5.  Any comments on cross-talk techniques?

I realize spreading traces out helps the most.  Other than running
HyperLynx's batch-mode simulation for cross-talk, any "procedure" or method
to the madness of simulating and observing cross-talk?

I look forward to your responses.  I've read all the app notes I can find
but I'd really like to hear from people who've made these kinds of designs
work.

Thanks a million for your help!

- Chuck
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