[SI-LIST] Re: DDR3 clock failing radiation Tests

I find that when EMI is this far out of compliance the problem is usually a
basic ground return path issue.
Possible sources are:

Insufficient ground pins/balls
Perforated planes in PCB or package
Uncontrolled DDR power or ground plane resonance.

These problems can sometimes be found by inspection by an expert.  A full
wave package/PCB solver can be used to perform an eigenmode analysis for
power/ground plane issues.

A solver like Ansoft SIwave can be useful for these analysis.

Happy hunting.

Scott
On Jan 7, 2012 7:26 PM, "Ken Wyatt" <ken@xxxxxxxxxxxxxxxx> wrote:

> Great reply Alfred - lots of good troubleshooting tips.
>
> Your comment on the PSA2701T caught my eye, as I've been using one of
> these for several years. However, few people have heard of the TTi Spectrum
> Analyzer, which is too bad. It's an incredible handheld (truly handheld!)
> instrument manufactured in the UK and distributed by Newark Electronics and
> Saelig Co. here in the US. Saelig actually has a slightly better price at
> $1,887. If anyone is interested in additional info on the TTi PSA2701T
> spectrum analyzer, I posted a comprehensive review on my web site:
> http://www.emc-seminars.com/Technical_Articles/files/TTi_PSA2701T_Spectrum_Analyzer_Wyatt.pdf
> .
>
> I'm also glad you referenced Doug Smith's web site. It's chock-full of
> high-frequency, EMC and ESD measurement techniques and tips. He's at:
> http://emcesd.com/
>
> By the way, anyone who registers for my free quarterly EMC newsletter will
> receive a link to a free list of troubleshooting tips, as well as all past
> newsletters. Click on the link below...
>
> References:
>
> Newark:
> http://www.newark.com/aim-tti-instruments/psa2701t/analyzer-spectrum-1mhz-to-2700mhz/dp/54M5938
>
> Saelig: http://www.saelig.com/category/TEEMCEE.htm
>
> Cheers, Ken
> _______________________
> Kenneth Wyatt
> Wyatt Technical Services LLC
> Woodland Park, CO
> Email Me! | Web Site | Blog
> Subscribe to Newsletter
> Connect with me on LinkedIn
>
> On Jan 7, 2012, at 1:16 PM, alfred1520list wrote:
>
> > Guess one more post does not alter the SNR significantly:)
> >
> > Quarter wave of 513 MHz in free space is 5.76", and roughly
> > half that in FR4.  I guess you don't happen to have a 3" tall
> > metal standoff that's mounted close to the ASIC to act as
> > an antenna, right?  Any way, controlled impedance traces aren't
> > efficient antenna compare to other physically large structure.
> > As some one else pointed out, common mode current can
> > couple to other physically large structures and they become
> > efficient radiator.  I find Doug has a few excellent papers
> > on EMI on his site:
> >
> > http://emcesd.com
> >
> > I find this particular interesting:
> >
> > "Current Probes, More Useful Than You Think":
> > http://emcesd.com/pdf/iprobe98.pdf
> >
> > One other suggestion from experience.  When you have 20 suspects
> > areas, it might be easier trying to make it worst to see which one
> > of them is the dominant source.  Even though all 20 suspects can all
> > radiate, probably only one of them is order of magnitude higher
> > than others.  If you can find that one and knock it down, you made
> > significant progress.  Since at 513 MHz it still needs significant
> physical
> > dimension (like an 1" long???) to radiate efficiently, use a piece of
> metal
> > like X-Acto knife, to touch everything and see if it make it worst.  Any
> > where you touch and made it worst is worth a closer look, especially
> > places where you don't expect, e.g. power supply, etc.
> >
> > Speaking of sniffing radiation, I have used PSA2701T:
> > http://www.tti-test.com/products-tti/rf/spectrum-analyzer.htm
> >
> > It's a great piece of gear and low enough in cost (a couple of US dollar
> as
> > I recall).  Since you aren't making certification measurement, you can
> > simply use any length of wire that register a reading at the frequency of
> > interest and make relative measurement.  I used a cheap US$30 discone
> > antenna.  If you make the spike smaller, you have made it better.
> >
> >
> > Best Regards,
> > Alfred Lee
> >
> > Web: www.mds.com
> >
> > ----- Original Message -----
> > From: "Eric Steimle" <eric.steimle@xxxxxxxxxx>
> > To: "vinod ah" <ah.vinod@xxxxxxxxx>; "SI-LIST" <si-list@xxxxxxxxxxxxx>
> > Sent: Saturday, January 07, 2012 11:27 AM
> > Subject: [SI-LIST] Re: DDR3 clock failing radiation Tests
> >
> >
> >> I agree that seeing the most emissions coming out of the ASIC is pretty
> common, especially if it's your ASIC ;), and unless you
> >> have some kind of crazy expensive (possible magic) software, simulation
> can't save you now.  I don't know what your application is
> >> but in the past I did a lot of unshielded consumer designs that used
> DDR2/3, and most  of them would not have made it through scan
> >> without spread spectrum.   I also agree that going to an expert EMI
> consultant could be well worth it, if your in NC I know a good
> >> one.
> >> Anyway I like to tackle emi problems by cutting everything into smaller
> and smaller pieces.  I don't know what your production
> >> options are but  here's one thing to try.  If you want to narrow things
> down you could build yourself a shield for your ASIC as a
> >> test.  Just get some Kapton tape, and some copper tape.  Kapton tape
> all around the ASIC, then copper tape over that.  Then ground
> >> the heck out of that copper tape, I usually do that by taking an exacto
> knife and cutting down to my gnd plane, but do what you
> >> can do.  After that sniff it again, or go pre-scan it if you can afford
> it.
> >>
> >> If that does nothing, at least you know you have additional problems
> elsewhere.  If it cleans it up, hurray just ship everything
> >> with copper tape.  Kidding but you could re-spin the board to
> accommodate a shield, and get the product out the door.
> >>
> >> This is just one of hundreds of things to try, but you asked for help
> finding the source.  The best advice I can give is to start
> >> eliminating things, by shielding / pulling parts off the board,
> changing clock frequencies, anything you can think of to narrow
> >> down the problem.   Keep track of how each change affects your
> emissions.  One time we ripped 12 ASICs off a large board and still
> >> had the problem! It was a lot easier to find without all those extra
> parts to question though.
> >>
> >> Good luck.
> >>
> >>
> >> Eric F. Steimle
> >> Hardware Engineering Manager
> >>
> >> +1 732-440-1280 x210 Office
> >> +1 732-212-9424 Fax
> >>
> >> 444 Route 35 South
> >> Building B
> >> Eatontown, NJ 07724 USA
> >>
> >> eric.steimle@xxxxxxxxxx
> >> www.altior.com
> >>
> >>
> >>
> >> ****Confidentiality Statement****
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> >> ________________________________________
> >> From: si-list-bounce@xxxxxxxxxxxxx [si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of vinod ah [ah.vinod@xxxxxxxxx]
> >> Sent: Saturday, January 07, 2012 12:27 AM
> >> To: SI-LIST
> >> Subject: [SI-LIST] DDR3 clock failing radiation Tests
> >>
> >> Hi all,
> >> I am facing problems related to EMI. I am having a ASIC with 2 DDR3
> >> controllers running at 513MHz clock. I am interfacing 2 memories to
> each of
> >> the controller. So totally 4 memory chips on board, all running at
> 513MHz
> >> clock. During pre-compliance radiation testing in FCC certified lab, we
> >> observed 513MHz in the spectrum with 15dB above the CISPR class B limits
> >> i.e. test failing by 15dB !!!!!
> >>
> >> I tried to corelate this result with Hyperlynx spectrum analyzer
> simulation
> >> and SI simulation. The waveforms and radiation level looks fine in
> >> Hyperlynx i.e. no issues seen. Initially i had suspected the layout, but
> >> hyperlynx SI simulation looks fine and also the clock & dqs waveforms in
> >> CRO looks fine i.e. no ringing/overshoot etc. The DDR3 clock is routed
> in
> >> inner layer 3 of six layer stack up of the board.
> >>
> >> I have tried using EMI shield, but still i am failing by 8dB. Only
> thing i
> >> have not yet tried is spread spectrum clocking. But I am unable to find
> the
> >> source of problem. Can you please help me out in finding the sourceto
> this
> >> problem.
> >>
> >> I understand that it is very tuff to provide solution to this problem
> >> without seeing the layout, but i am expecting some tips so that i can
> move
> >> ahead in debugging the problem.
> >>
> >> Regards
> >> Vinod A H
> >>
> >>
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