[SI-LIST] Re: DDR2-optimal timing
- From: "Kishan Chowhan" <kschowhan@xxxxxxxxx>
- To: rajasekar_d2003@xxxxxxxxxxx
- Date: Tue, 21 Mar 2006 22:42:45 +0530
Hi Rajasekar,
Please refer to JEDEC spec. (JESD79-2A),which has input slew rate tables
for DDR2 to allow more accurate estimation of setup and hold time margin.
A thorough timing analysis is needs to be done for DDR2 interface.Assuming a
PowerPC interface ,it has configuration register to introduce delay in DQS
signal to get the minimum trace delay.
Regards,
Kishan
On 3/21/06, Rajasekar <rajasekar_d2003@xxxxxxxxxxx> wrote:
>
> Hi,
>
> What are parameters need to be considered, while operating DDR2
> interface at 133MHZ clock for 200 pin DDR2 SDRAM SO-DIMM
> (MT4HTF3264HY-40EB4) device?
>
> could you please suggest the optimal timing configuration ?
>
> I want to ensure the Corner case cycle timing for all the configurable
> parameters for this DDR module with 133MHZ clock rate.
>
> Please advice,
>
> thanks,
> Rajasekar
>
>
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- References:
- [SI-LIST] DDR2-optimal timing
- From: Rajasekar
Other related posts:
- » [SI-LIST] DDR2-optimal timing
- » [SI-LIST] Re: DDR2-optimal timing
- » [SI-LIST] Re: DDR2-optimal timing
- [SI-LIST] DDR2-optimal timing
- From: Rajasekar