[SI-LIST] Re: DDR2 termination Questions
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: hitheshn@xxxxxxxxx
- Date: Sat, 28 Apr 2012 15:42:58 +0200
Hello Hithesh,
If your FPGA provides an OnDie Termination (what I would expect and
somehowr read from your e-mail) usually there is no need for additional
Series termination on the PCB. Is there any specific reason why you want
to add this resistor ?
The termination to midlevel (VTT) is part of the spec. Reasons why DRAM
interconnects are not terminated to GND are the process technology of
DRAMs (this would even prefer a high level termination) and the Point to
multipoint communiction on DRAM busses (if your drivestrength is always
the same, but different numbers of DRAMs are terminating this will
shift your eye center level. if all DRAMs terminate to midlevel the Eye
center voltage will be the same (just the swing will change).
your voltage swing will be symmetrical arround VTT. And the hight will
depend on drivestrength and termination settings. As Steve mentioned the
swing can be calculated when you draw the circuit.
Hermann
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schrieb Hithesh:
> Some questions about DDR2 termination -
> Let's say it's a Read operation from Memory to FPGA
>
> DDR2 ---> series termination res--->50 ohm PCB Tx line -->50 ohm
> termination resistor at FPGA to Vtt.
>
> Why should the 50 ohm resistor be terminated to Vtt, why not ground (like
> RF amplifiers)?
>
> Is the DDR2 output voltage 1.8v? If yes, then the max voltage at FPGA will
> be 0.9v.
>
> Thanks,
> -Hithesh
>
>
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