[SI-LIST] Re: DDR2 termination Questions
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sat, 28 Apr 2012 05:19:03 -0700
I think you should draw the circuit: The way that it is, and other
configurations that you might try. See what happens to the DC bias
voltage and current for each combination for both a high and a low
state. That will answer both your questions.
Steve.
On 4/28/2012 5:07 AM, Hithesh wrote:
> Some questions about DDR2 termination -
> Let's say it's a Read operation from Memory to FPGA
>
> DDR2 ---> series termination res--->50 ohm PCB Tx line -->50 ohm
> termination resistor at FPGA to Vtt.
>
> Why should the 50 ohm resistor be terminated to Vtt, why not ground (like
> RF amplifiers)?
>
> Is the DDR2 output voltage 1.8v? If yes, then the max voltage at FPGA will
> be 0.9v.
>
> Thanks,
> -Hithesh
>
>
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