[SI-LIST] Re: DDR2 inteface consultant needed

I do not use DCI, I tried DCI driver as well with the same effect. The 
only difference was that amplitude of output signal was slightly reduced.

I have also tried LVCMOS 1.8V-16mA-Fast and I terminated it to 0.9V at 
the end of a line. The result was similar to SSTL18-I/SSTL18-II driver: 
there was a shelf on the rising edge. I tested LVCMOS25-24-Fast driver 
(another FPGA bank) terminated to 1.25V and I didn't have this issue. 
There was an idea to change Vdd of the bank which suffers the problem 
from 1.8V to 2.5V and to see what happens but it is not straight forward 
(other devices use the same 1.8V) so it wasn't done.

Have you used Spartan3 with 1.8V IOs terminated by Thevenin termination.

thank you for suggestions,
Robert


Chris Johnson wrote:
> Robert,
>
> Are you using the Spartan DCI?  If so, do you have VRP and VRN 
> resistors connected correctly?  VRP goes to ground and VRN goes to 
> VCCO (1.8V).  Are the resistor values correct?
>
> You could try temporarily disabling DCI and changing the I/O type to 
> straight 1.8V LVCMOS to see if it makes a difference.  That would at 
> least verify that the problem is related to the driver on the Spartan.
>
> Chris
>
> Robert Szumowicz wrote:
>> This DDR2 clock issue is interesting and it worries for me.  I have 
>> done very extensive testing of this issue (2.5GHz scope, 1.5GHz fet 
>> probes, 1.7 GHz diff probes, homemade resistive probes, GND loop is 
>> always minimized). I tested it with different memory modules with 
>> chips on them from different manufacturers and even without memory at 
>> all (but then I needed to terminate the clocks on my board). It seems 
>> that (at least in my case) Spartan3 drives signals powered from 1.8V 
>> in a strange way:
>>  - falling edge is a clean transaction from HI to LOW state
>>  - rising edge is strange it seems that at first it goes to HiZ state 
>> and after some time it is driven HI
>>
>> I have done the following tests:
>>
>> First test was done without memory (so there was no differential 
>> termination between lines and they didn't branch), each line of the 
>> differential clock pair was terminated by 50Ohm to GND then I 
>> captured waveforms at the terminators (end of line). I observed that 
>> complementary output does not follow the positive output.
>>
>>
>> Then I took one line of the differential pair, stimulated it using a 
>> clock signal, I again removed the memory module and terminated the 
>> line at the very end to Vtt (1/2 VDD). The result was that I got a 
>> 'shelf' at Vtt level. That shelf lasted for about 1ns (quite long). 
>> Then I terminated the same line to GND and as a result I got no shelf 
>> but duty cycle distortion, i.e. line was in LOW state longer than in 
>> HI state.
>>
>> The art drawing shows the measurements.
>>
>>                   +--------+
>>                   |        |
>>                +--+        |
>>   term to VTT  |           |
>>        --------+           +------
>>
>>                   +--------+
>>                   |        |
>>                   |        |
>>   term to GND     |        |
>>         ----------+        +------
>>
>>
>> It seems to me that all SSTL18 signals driven by my Spartan3 are 
>> affected by this phenomena. Since most of signals have a series 
>> termination 22R on the memory module it helps a little to 'smooth' 
>> the shelf, probably by creating a low pass filter together with a 
>> load capacitance. Differential clock signals do not have this series 
>> resistance placed close to load and they look very distorted. I think 
>> that for some time one signal from the pair is not driven by FPGA but 
>> only by differential terminator at the very end of the line (and by 
>> strong driver of a complementary signal). As I mentioned before 
>> differentially this clock signal looks good.
>>
>> The question is whether it may create some problems or can I live 
>> with it?
>>
>>
>> Regarding the crosstalk. I tried to measure it and to find sources of 
>> it. It is very hard to correlate this crosstalk with PCB, I suppose 
>> that majority of it comes form the controller itself (the strongest 
>> aggressors are the neighboring FPGA pins not always neighboring PCB 
>> traces).
>>
>> I have one question to the group regarding a crosstalk: If two lines 
>> (victim and aggressor) are routed as strip lines and the victim has 
>> series terminator at the beginning of the line should we observe a 
>> crosstalk at the end of the victim line? My understanding is that in 
>> an ideal situation we shouldn't see any crosstalk at the victim's end 
>> because in such configuration there is no FEXT and NEXT which is 
>> inducted does not reflect back from the beginning of the line because 
>> it is absorbed by the termination (Rs+driver resistance) so it does 
>> not appear at the end of victim.
>>
>> thanks,
>> Robert Szumowicz
>>  
>

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