[SI-LIST] Re: DDR2 design

Chris, FPGAs are getting better, but they don't make this 
simple.  That is why the "A" and "X" companies have both worked 
pretty hard to develop kits that greatly simplify the design 
tasks.  The timing margins just aren't as luxurious as with other 
parts.  Flexibility comes at a price.

Depending on the component, turning on ODT causes timing problems 
that prevent operation at 333 or above.  I don't know where the 
current Cyclone parts sit on that.  I/O floor planning, and 
board  stack-up are also major influences on cross talk related timing.

Ivor needs to plan and simulate the channel, including the FPGA timing budget.

Best Regards,


Steve

At 06:00 PM 2/22/2006, Chris Cheng wrote:
>I am sorry, that is a point to point data/strobe bus on the motherboard
>without socket at 333MHz, right ? If you turn on ODT and match length,
>how hard can it be ?
>How hard can it be for a uni-directional control line only 4 inches
>long, how hard can it be ?
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ivor Bowden
>Sent: Wednesday, February 22, 2006 3:22 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] DDR2 design
>
>
>Hi SI Experts,
>
>I am reviewing a layout for an embedded DDR2 design using 4 Micron DDR2=20
>chips with an Altera Cyclone controller. The memory is set up to be 64=20
>bits wide, 16 bits per chip.
>
>The target rate is 167MHz. The design is not simulated.
>
>Termination is as follows:
>ODT may be supported, still investigating.
>There is no series term.
>There is 0.9V stub term for control lines.
>There is a differential 100 ohm term for each clock pair (4 total).
>
>Routing is as follows:
>Control lines are daisy chained and length matched between the first=20
>DRAM and controller (about 1"), each DRAM (about .75") and the last DRAM
>
>and terminators (about .25"); total net length is about 3.5".
>Data lines are length matched at about 3" (controller to DRAM).
>Clock lines are length matched at about 4" (controller to DRAM).
>Trace impedance is targeted at 100 ohms for clock and control lines, and
>
>75 ohms for data lines.
>
>Is this design likely to work? If not, what changes should be
>considered?
>
>I very much appreciate all comments. Thank you!
>
>Ivor Bowden
>Engineer
>Curtiss-Wright Controls
>
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