[SI-LIST] Re: DDR2 design

Generalizing a little bit (and not directed to Ivor), the best the
SIList can do is help you understand that you might have a problem. If
you're going to be successful with the design and make, not lose, $$ for
your company, then you still have to dive into the details and solve the
problem the List helped you to see.=20

Besides the excellent suggestions regarding SI simulation, there are
also some timing problems that you'll need to dive in and understand.
one of them (mentioned below), is the Control Bus timing. the other one
is the data bus (DQ) timing. In both you have to establish how you move
the clock (either CK or DQS) into the middle of the data/control bus
"eye". And with a Read data transaction you have to figure out how to
cross back into the controller's internal clock domain. (whether or not
you use a "Design Kit" from somebody, you should understand the timing
solution.)

regards,
Jim Peterson
Honeywell=20

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Jai Shanker
Sent: Thursday, February 23, 2006 2:24 AM
To: ivorlist@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR2 design

Hi Ivor,

I am a novice here but we did a couple of similar designs - one with a
Xilinx FPGA but much lower frequency (~100Mhz clock) and another with an
ASIC at 267Mhz.=20

We used 50 ohm lines and tightly matched the lengths (maybe a little
overconstrained for safety). I think there is a clock to address/
control relationship that you may have overlooked ( or maybe not, from
your length reports). Have you deliberately set the clock length to be
greater then the address/ control length.

However it is always better to simulate. We did.=20

With the FPGAs, you may need to watch out for crosstalk. A Xilinx SSO
calculator gave us only about 45% of the IOs within a bank as usable
outputs.=20

regards,
Jai
--- Ivor Bowden <ivorlist@xxxxxxxxxxx> wrote:

> Hi SI Experts,
>=20
> I am reviewing a layout for an embedded DDR2 design using 4 Micron=20
> DDR2 chips with an Altera Cyclone controller. The memory is set up to=20
> be 64 bits wide, 16 bits per chip.
>=20
> The target rate is 167MHz. The design is not simulated.
>=20
> Termination is as follows:
> ODT may be supported, still investigating.
> There is no series term.
> There is 0.9V stub term for control lines.
> There is a differential 100 ohm term for each clock pair (4 total).
>=20
> Routing is as follows:
> Control lines are daisy chained and length matched between the first=20
> DRAM and controller (about 1"), each DRAM (about
> .75") and the last DRAM
> and terminators (about .25"); total net length is about 3.5".
> Data lines are length matched at about 3"
> (controller to DRAM).
> Clock lines are length matched at about 4"
> (controller to DRAM).
> Trace impedance is targeted at 100 ohms for clock and control lines,=20
> and
> 75 ohms for data lines.
>=20
> Is this design likely to work? If not, what changes should be=20
> considered?
>=20
> I very much appreciate all comments. Thank you!
>=20
> Ivor Bowden
> Engineer
> Curtiss-Wright Controls
>=20
>
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