[SI-LIST] Re: DDR2 design

Hi Ivor,

I am a novice here but we did a couple of similar
designs - one with a Xilinx FPGA but much lower
frequency (~100Mhz clock) and another with an ASIC at
267Mhz. 

We used 50 ohm lines and tightly matched the lengths
(maybe a little overconstrained for safety). I think
there is a clock to address/ control relationship that
you may have overlooked ( or maybe not, from your
length reports). Have you deliberately set the clock
length to be greater then the address/ control length.

However it is always better to simulate. We did. 

With the FPGAs, you may need to watch out for
crosstalk. A Xilinx SSO calculator gave us only about
45% of the IOs within a bank as usable outputs. 

regards,
Jai
--- Ivor Bowden <ivorlist@xxxxxxxxxxx> wrote:

> Hi SI Experts,
> 
> I am reviewing a layout for an embedded DDR2 design
> using 4 Micron DDR2 
> chips with an Altera Cyclone controller. The memory
> is set up to be 64 
> bits wide, 16 bits per chip.
> 
> The target rate is 167MHz. The design is not
> simulated.
> 
> Termination is as follows:
> ODT may be supported, still investigating.
> There is no series term.
> There is 0.9V stub term for control lines.
> There is a differential 100 ohm term for each clock
> pair (4 total).
> 
> Routing is as follows:
> Control lines are daisy chained and length matched
> between the first 
> DRAM and controller (about 1"), each DRAM (about
> .75") and the last DRAM 
> and terminators (about .25"); total net length is
> about 3.5".
> Data lines are length matched at about 3"
> (controller to DRAM).
> Clock lines are length matched at about 4"
> (controller to DRAM).
> Trace impedance is targeted at 100 ohms for clock
> and control lines, and 
> 75 ohms for data lines.
> 
> Is this design likely to work? If not, what changes
> should be considered?
> 
> I very much appreciate all comments. Thank you!
> 
> Ivor Bowden
> Engineer
> Curtiss-Wright Controls
> 
>
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