[SI-LIST] Re: DDR2 Trace Length Margin

Hi Lee,

I was out of town this week and just had a chance to see your post. Our
recommendation for +/20 mils is based on feedback from CAD team, that
its just as easy to match to 20 mils as it is to 100 mils, therefore, we
feel its best to preserve as much margin as possible. Sure its true that
any given design might work with a looser spacing, but why leave margin
on the table.  At least that is my opinion. If someone feels strongly
that meeting those requirements requires undue effort of excessive
serpentine, then make a different choice. I'm just conveying the
rational for my original statement. I did not mean to imply that +/-20
mils was required to make the typical design work. =20


Brian Moran
MPG/MPHD/EDE/PEA Group
Intel Corporation

-----Original Message-----
From: Dan Smith [mailto:Dan.Smith@xxxxxxxxx]=20
Sent: Thursday, July 24, 2008 9:21 AM
To: Lee Ritchey; Moran, Brian P; sreekanthn; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: DDR2 Trace Length Margin

The last DDR-2 design I did I had DQS and DQ matched to as sloppy as 1"
and I still had 15% margin on reads and over 50% margins on writes - and
this included PCB impedance variations and loss due to reflections.  I
implemented more strict rules than 1" but to me, +/- 20 mils is a way
over burden on the CAD designer.

Danno

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Thursday, July 24, 2008 9:06 AM
To: Moran, Brian P; sreekanthn; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR2 Trace Length Margin

Length matching to +/- 20 mils means length matching to 3.2 pSec.  That
is
unrealistically tight.    Why not couch length matching in terms of time
tolerance and then allow designers to turn this into length.

I match 2.4 Gb/S differential paths to +/- 150 mils or +/- 24 pS.  How
could DDR2 require tighter than that or even that tight?

Lee Ritchey


> [Original Message]
> From: Moran, Brian P <brian.p.moran@xxxxxxxxx>
> To: sreekanthn <sreekanthn@xxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 7/21/2008 9:27:41 PM
> Subject: [SI-LIST] Re: DDR2 Trace Length Margin
>
> Hi Sreekanth,
>
> There is no single specification for length matching.  You generally
> need to simulate and
> do an AC analysis of each application.  However, I can give you some
> general rules of thumb
> from our DDR2 design guides. However, our guidelines are based on
> motherboard rules to the module
> connector. If your SDRAMs are down on the motherboard, then you do not
> need to account for
> the length variation on the modules.  Which should give you slightly
> looser rules then our
> guidelines stipulate.=3D20
>
> The length matching between DQ and DQS within a byte lane is the
> tightest constraint. Here
> we receommend +/- 20 mils, but this might be overkill in some cases.
I
> would recommend no
> more than +/-50 between DQs and their associated DQS strobe.=3D20
>
> The length matching between CTRL and CLK and between ADR/CMD and CLK
is
> much looser in terms
> of the length window, but the relative offset between each of these
> groups and CLK must be
> adjusted in some cases, in order to center the valid window.  This
> offset is very much dependent
> on the controller timing. Most controller allow this to be done
through
> register control.=3D20
>
> But is terms of the length mismatch windows you can generally live
with
> a length window of 1.0"=3D20
> (+/- 0.5") on CTRL to CLK, and perhaps 2.0" (+/-1.0") on ADR/CMD to
CLK,
> assuming you are using
> 2N timing on ADR/CMD.
>
> DQS to CLK is also constrained. Here the overall length window is
> generally 1.0" to 1.5" wide.=3D20
>
>
> So you start by routing and length matching your CLKs.  Then establish
> your length window around CLK
> for CTRL, CMD, and DQS.  If you find it hard to route within these
> windows, then lengthen CLKs as required
> to get the length window in the required range.  Usually this is
> dictated by the min and max length of
> the DQS strobes, since the DQ bus has the largest natural length
> variation between the shortest byte lanes
> and the longest. =3D20
>
> The controllers generally have a timing offset control that will allow
> you to optimize setup and hold
> by shifting CLK, CTRL and CMD, at the source. =3D20
> =3D20
>
>
> Brian Moran
> MPG/MPHD/EDE/PEA Group
> Intel Corporation
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of sreekanthn
> Sent: Monday, July 21, 2008 5:07 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR2 Trace Length Margin
>
>
>
> Hi Experts,
>
> I would like to know the length matching requirement of a  DDR2
design.
> I have two memory devices in my board (NOT DIMMs).
> Each has 16 bit data (Total 32) ,Each byte has its own Data strobe and
> Mask
> signals.
>
> Datas ,Stobes,Masks,Clk etc are point to point topology.
> Address and other common signals ( RAS,CAS,WE,RE,CS,CLKEN etc...)  has
> to be
> routed in T topology.
>
> Could someone please explain the rule of length matching for each
> groups.
> Is there any standard docs available ? I refered JDEC  specs, I could
> n't
> get any routing recommendations.
>
> How can we engineer the trace length margin ?
>
> My Max clock would be 667MHz.
>
> Regards,
> Sreekanth=3D20
>
>
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