[SI-LIST] Re: DDR2 Trace Length Margin

Aubrey's later example is a good one, though.  For the majority of=0A=
designs that I do, the advantages of "over-constraining" outweigh the=0A=
negatives.  That hasn't always been true, and I've gone through the=0A=
analysis in those minority cases, but it is generally.  While it might=0A=
be interesting for me to do a series of simulations and measurements in=0A=
a complex experiment to determine exactly how much trace mismatch I can=0A=
tolerate on every design, it's not very practical.  I'm quicker to=0A=
market by bounding that mismatch at some reasonable and conservative=0A=
level and spending my time analyzing parts of the design where the=0A=
tradeoff is less clear and my expertise is therefore better utilized.=0A=
=0A=
Not too many people ship systems with no margin, so we're really asking=0A=
what level of overkill is too much.  The debate, which we've had on this=0A=
list multiple times over the years, is by how much, and the follow-on=0A=
question is how much time and energy is it worth to reduce that amount=0A=
of overkill.=0A=
=0A=
robert=0A=
=0A=
-----Original Message-----=0A=
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]=0A=
On Behalf Of Scott McMorrow=0A=
Sent: Thursday, July 24, 2008 3:57 PM=0A=
To: Aubrey_Sparkman@xxxxxxxx=0A=
Cc: leeritchey@xxxxxxxxxxxxx; jeff.loyer@xxxxxxxxx; Dan.Smith@xxxxxxxxx;=0A=
si-list@xxxxxxxxxxxxx=0A=
Subject: [SI-LIST] Re: DDR2 Trace Length Margin=0A=
=0A=
Well, the other possibility is that a proper analysis was not considered=0A=
to be important.=0A=
=0A=
Scott McMorrow=0A=
Teraspeed Consulting Group LLC=0A=
121 North River Drive=0A=
Narragansett, RI 02882=0A=
(401) 284-1827 Business=0A=
(401) 284-1840 Fax=0A=
=0A=
http://www.teraspeed.com=0A=
=0A=
Teraspeed(r) is the registered service mark of Teraspeed Consulting=0A=
Group LLC=0A=
=0A=
=0A=
=0A=
Aubrey_Sparkman@xxxxxxxx wrote:=0A=
> Lee,=0A=
>=0A=
> So you think the only reason someone would not do what you consider=20=0A=
> proper analysis is because they are lazy?=3D20=0A=
>=0A=
>=0A=
> Aubrey Sparkman=3D20=0A=
> Enterprise Engineering Signal Integrity Team=3D20 Dell, Inc.=3D20=20=0A=
> Aubrey_Sparkman@xxxxxxxx=3D20=0A=
> (512) 723-3592=3D20=0A=
> "The single biggest problem in communication is the illusion that it=20=
=0A=
> has taken place." -- George Bernard Shaw=0A=
>=0A=
>=0A=
>=0A=
> -----Original Message-----=0A=
> From: si-list-bounce@xxxxxxxxxxxxx=20=0A=
> [mailto:si-list-bounce@xxxxxxxxxxxxx]=0A=
> On Behalf Of Lee Ritchey=0A=
> Sent: Thursday, July 24, 2008 1:17 PM=0A=
> To: Jeff Loyer; Dan Smith; si-list@xxxxxxxxxxxxx=0A=
> Subject: [SI-LIST] Re: DDR2 Trace Length Margin=0A=
>=0A=
> The problem with inserting add length arbitrarily is what it does to=20=
=0A=
> the routing surface.  I've seen messes around DDR2 sockets that are=20=20=
=0A=
> totally unnecessary and use board space that cold well be used for=0A=
other things.=0A=
>=0A=
> Add length is not free nor does it take zero time.  It should be used=20=
=0A=
> only when necessary, not when engineers are too lazy to do proper=20=0A=
> analysis.=3D20=0A=
>=0A=
>=0A=
>=20=20=20=0A=
>> [Original Message]=0A=
>> From: Loyer, Jeff <jeff.loyer@xxxxxxxxx>=0A=
>> To: Dan Smith <Dan.Smith@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>=0A=
>> Date: 7/24/2008 10:28:16 AM=0A=
>> Subject: [SI-LIST] Re: DDR2 Trace Length Margin=0A=
>>=0A=
>> In my experience, CAD folks have constantly fed back that, if I'm=3D20=
=20=0A=
>> going to constrain the lengths, there's not much difference=20=0A=
>> between=3D20 matching to within 100 mils or 5.  Based on that, we often=
=0A=
=0A=
>> put the=3D20 constraints to=0A=
>> 5 mils, even though that number appears ridiculously tight.  It=20=0A=
>> also=3D20 allows them to keep constraints consistent throughout a=20=0A=
>> design, and=3D20 less prone to error.  And, if it's over-tight, we=20=0A=
>> don't have to worry=3D20 about how much of the length matching gets=20=
=0A=
>> applied to each board (of a=0A=
>>=20=20=20=20=20=0A=
>=0A=
>=20=20=20=0A=
>> multi-board design).=0A=
>>=0A=
>> For me, it allows me to ignore length matching as a variable in my=3D20=
=0A=
=0A=
>> design; another place I don't have to expend energy.  Instead, I=20=0A=
>> can=3D20 spend it on things that are challenging and critical.=0A=
>>=0A=
>> Yes, you are correct that often the constraints appear absurd.=20=20=0A=
>> But,=3D20 there are practical reasons for having those tight=20=0A=
>> constraints.  If=3D20 there were significant challenges at meeting the=
=20=0A=
>> tight numbers, often=3D20 some back-of-the-envelope calculations can be=
=0A=
=0A=
>> used to provide=3D20 relaxation.=0A=
>>=0A=
>> This paradigm has been in place for years, with FSB length=20=0A=
>> matching=3D20 rules of within 10 mils, for instance.  Yes, the design=20=
=0A=
>> could tolerate=0A=
>>=20=20=20=20=20=0A=
>=0A=
>=20=20=20=0A=
>> much more, but CAD folks had little problem meeting it, and it=20=0A=
>> made=3D20 length matching a moot point.=0A=
>>=0A=
>> Disclaimer:=0A=
>> The content of this message is my personal opinion only and although=20=
=0A=
>> I=0A=
>>=20=20=20=20=20=0A=
>=0A=
>=20=20=20=0A=
>> am an employee of Intel, the statements I make here in no way=3D20=20=0A=
>> represent Intel's position on the issue, nor am I authorized to=20=0A=
>> speak=3D20 on behalf of Intel on this matter.=0A=
>>=0A=
>> Jeff Loyer=0A=
>>=0A=
>> -----Original Message-----=0A=
>> From: si-list-bounce@xxxxxxxxxxxxx=3D20=20=0A=
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]=0A=
>> On Behalf Of Dan Smith=0A=
>> Sent: Thursday, July 24, 2008 9:21 AM=0A=
>> To: Lee Ritchey; Moran, Brian P; sreekanthn; si-list@xxxxxxxxxxxxx=0A=
>> Subject: [SI-LIST] Re: DDR2 Trace Length Margin=0A=
>>=0A=
>> The last DDR-2 design I did I had DQS and DQ matched to as sloppy as=0A=
>>=20=20=20=20=20=0A=
> 1"=0A=
>=20=20=20=0A=
>> and=3D3D3D=0A=
>>  I still had 15% margin on reads and over 50% margins on writes -=20=0A=
>> and=3D20 this =3D3D3D included PCB impedance variations and loss due=20=
=0A=
>> to=3D20 reflections.  I implement=3D3D3D ed more strict rules than 1" but=
=0A=
=0A=
>> to me, =3D=0A=
>>=20=20=20=20=20=0A=
>=0A=
>=20=20=20=0A=
>> +/- 20 mils is a way over burden on=3D3D3D  the CAD designer.=0A=
>>=0A=
>> Danno=0A=
>>=0A=
>> -----Original Message-----=0A=
>> From: si-list-bounce@xxxxxxxxxxxxx=3D20=20=0A=
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]=0A=
>> On=3D3D3D=0A=
>>  Behalf Of Lee Ritchey=0A=
>> Sent: Thursday, July 24, 2008 9:06 AM=0A=
>> To: Moran, Brian P; sreekanthn; si-list@xxxxxxxxxxxxx=0A=
>> Subject: [SI-LIST] Re: DDR2 Trace Length Margin=0A=
>>=0A=
>> Length matching to +/- 20 mils means length matching to 3.2 pSec. =3D20=
=0A=
=0A=
>> That is=0A=
>> unrealistically tight.    Why not couch length matching in terms of=0A=
>>=20=20=20=20=20=0A=
> time=0A=
>=20=20=20=0A=
>> tolerance and then allow designers to turn this into length.=0A=
>>=0A=
>> I match 2.4 Gb/S differential paths to +/- 150 mils or +/- 24 pS.=20=20=
=0A=
>> How=0A=
>>=20=20=20=20=20=0A=
>=0A=
>=20=20=20=0A=
>> could DDR2 require tighter than that or even that tight?=0A=
>>=0A=
>> Lee Ritchey=0A=
>>=0A=
>>=0A=
>>=20=20=20=20=20=0A=
>>> [Original Message]=0A=
>>> From: Moran, Brian P <brian.p.moran@xxxxxxxxx>=0A=
>>> To: sreekanthn <sreekanthn@xxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>=0A=
>>> Date: 7/21/2008 9:27:41 PM=0A=
>>> Subject: [SI-LIST] Re: DDR2 Trace Length Margin=0A=
>>>=0A=
>>> Hi Sreekanth,=0A=
>>>=0A=
>>> There is no single specification for length matching.  You generally=0A=
>>>=20=20=20=20=20=20=20=0A=
>=0A=
>=20=20=20=0A=
>>> need to simulate and do an AC analysis of each application. =3D20=20=0A=
>>> However, I can give you some general rules of thumb from our DDR2=3D20=
=0A=
=0A=
>>> design guides. However, our guidelines are based on motherboard=3D20=20=
=0A=
>>> rules to the module connector. If your SDRAMs are down on the=3D20=20=
=0A=
>>> motherboard, then you do not need to account for the length=3D20=20=0A=
>>> variation on the modules.  Which should give you slightly looser=3D20=
=20=0A=
>>> rules then our guidelines stipulate.=3D3D3D3D20=0A=
>>>=0A=
>>> The length matching between DQ and DQS within a byte lane is the=3D20=
=20=0A=
>>> tightest constraint. Here we receommend +/- 20 mils, but this=20=0A=
>>> might=3D20 be overkill in some cases.=0A=
>>>=20=20=20=20=20=20=20=0A=
>> I=0A=
>>=20=20=20=20=20=0A=
>>> would recommend no=0A=
>>> more than +/-50 between DQs and their associated DQS =3D=0A=
>>>=20=20=20=20=20=20=20=0A=
> strobe.=3D3D3D3D20=0A=
>=20=20=20=0A=
>>> The length matching between CTRL and CLK and between ADR/CMD and CLK=0A=
>>>=20=20=20=20=20=20=20=0A=
>> is=0A=
>>=20=20=20=20=20=0A=
>>> much looser in terms=0A=
>>> of the length window, but the relative offset between each of=20=0A=
>>> these=3D20 groups and CLK must be adjusted in some cases, in order to=
=20=0A=
>>> center=3D20 the valid window.  This offset is very much dependent on=20=
=0A=
>>> the=3D20 controller timing. Most controller allow this to be done=0A=
>>>=20=20=20=20=20=20=20=0A=
>> through=0A=
>>=20=20=20=20=20=0A=
>>> register control.=3D3D3D3D20=0A=
>>>=0A=
>>> But is terms of the length mismatch windows you can generally live=0A=
>>>=20=20=20=20=20=20=20=0A=
>> with=0A=
>>=20=20=20=20=20=0A=
>>> a length window of 1.0"=3D3D3D3D20=0A=
>>> (+/- 0.5") on CTRL to CLK, and perhaps 2.0" (+/-1.0") on ADR/CMD to=0A=
>>>=20=20=20=20=20=20=20=0A=
>> CLK,=0A=
>>=20=20=20=20=20=0A=
>>> assuming you are using=0A=
>>> 2N timing on ADR/CMD.=0A=
>>>=0A=
>>> DQS to CLK is also constrained. Here the overall length window is=3D20=
=0A=
=0A=
>>> generally 1.0" to 1.5" wide.=3D3D3D3D20=0A=
>>>=0A=
>>>=0A=
>>> So you start by routing and length matching your CLKs.  Then=3D20=20=0A=
>>> establish your length window around CLK for CTRL, CMD, and DQS.=20=20=
=0A=
>>> If=3D20 you find it hard to route within these windows, then lengthen=
=20=0A=
>>> CLKs=3D20 as required to get the length window in the required range.=
=0A=
=0A=
>>> Usually=0A=
>>>=20=20=20=20=20=20=20=0A=
>=0A=
>=20=20=20=0A=
>>> this is dictated by the min and max length of the DQS strobes, since=0A=
>>>=20=20=20=20=20=20=20=0A=
>=0A=
>=20=20=20=0A=
>>> the DQ bus has the largest natural length variation between the=3D20=20=
=0A=
>>> shortest byte lanes and the longest. =3D3D3D3D20=0A=
>>>=0A=
>>> The controllers generally have a timing offset control that will=3D20=
=20=0A=
>>> allow you to optimize setup and hold by shifting CLK, CTRL and=20=0A=
>>> CMD,=3D20 at the source. =3D3D3D3D20 =3D3D3D3D20=0A=
>>>=0A=
>>>=0A=
>>> Brian Moran=0A=
>>> MPG/MPHD/EDE/PEA Group=0A=
>>> Intel Corporation=0A=
>>>=0A=
>>> -----Original Message-----=0A=
>>> From: si-list-bounce@xxxxxxxxxxxxx=0A=
>>>=20=20=20=20=20=20=20=0A=
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]=0A=
>>=20=20=20=20=20=0A=
>>> On Behalf Of sreekanthn=0A=
>>> Sent: Monday, July 21, 2008 5:07 AM=0A=
>>> To: si-list@xxxxxxxxxxxxx=0A=
>>> Subject: [SI-LIST] DDR2 Trace Length Margin=0A=
>>>=0A=
>>>=0A=
>>>=0A=
>>> Hi Experts,=0A=
>>>=0A=
>>> I would like to know the length matching requirement of a  DDR2=0A=
>>>=20=20=20=20=20=20=20=0A=
>> design.=0A=
>>=20=20=20=20=20=0A=
>>> I have two memory devices in my board (NOT DIMMs).=0A=
>>> Each has 16 bit data (Total 32) ,Each byte has its own Data=20=0A=
>>> strobe=3D20 and Mask signals.=0A=
>>>=0A=
>>> Datas ,Stobes,Masks,Clk etc are point to point topology.=0A=
>>> Address and other common signals ( RAS,CAS,WE,RE,CS,CLKEN etc...)=20=0A=
>>> =3D20 has to be routed in T topology.=0A=
>>>=0A=
>>> Could someone please explain the rule of length matching for each=3D20=
=0A=
=0A=
>>> groups.=0A=
>>> Is there any standard docs available ? I refered JDEC  specs, I=3D20=20=
=0A=
>>> could n't get any routing recommendations.=0A=
>>>=0A=
>>> How can we engineer the trace length margin ?=0A=
>>>=0A=
>>> My Max clock would be 667MHz.=0A=
>>>=0A=
>>> Regards,=0A=
>>> Sreekanth=3D3D3D3D20=0A=
>>>=0A=
>>>=0A=
=0A=
--=20=0A=
Email scanned by DoubleCheck=0A=
http://www.nmgi.com/doublecheck/=0A=
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