[SI-LIST] DDR2 Setup/Hold Derating

Hi,
 

I have a situation in which the input slew rate at the DDR2 memory device is
well above the coverage of the tables for both the CLK/DQS signals and the
CMND/ADDR/DQ signals. When I say well above the table coverage, some are as
high as 9V/ns. The combination of high slew rates on all signals pushes me
way outside the table to the north-west, somewhere near Anchorage when I'm
shooting for Denver!

 

I know the rule is to linearly extrapolate the setup/hold numbers based on
the last two entries in the table (easy enough when going in one direction
outside of the table) but I'd like to know if anyone has any advice for,
what I consider, a rather extreme situation as this. Is it sound practice to
continue the extrapolation this far from the table? Should I consider ways
to try and reduce the slew rate (e.g. tinkering with the termination scheme
and values, provided I keep up the signal quality and threshold margins)?

 

Thanks!

Tony



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