[SI-LIST] Re: DDR-2 DQS

  • From: Vinu Arumugham <vinu@xxxxxxxxx>
  • To: jellis@xxxxxxxxx
  • Date: Tue, 14 Oct 2003 17:57:32 -0700

Pg. 69 of the spec. has:

"NOTE 4   Differential data strobe.  DDR2 SDRAM pin timings are 
specified for either single ended mode or differential
mode depending on the setting of the EMRS "Enable DQS" mode bit; timing 
advantages of differential mode are real-
ized in system design. The method by which the DDR2 SDRAM pin timings 
are measured is mode dependent. In sin-
gle ended mode, timing relationships are measured relative to the rising 
or falling edges of DQS crossing at VREF. In
differential mode, these timing relationships are measured relative to 
the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is guaranteed by design and 
characterization. When differential data strobe mode is
disabled via the EMRS, the complementary pin, DQS, must be tied 
externally to VSS through a 20  to 10K  resistor
to insure proper operation."

Suggests true differential receivers that switch at the crosspoint?

Thanks,
Vinu



John Ellis wrote:

>Hi Steve,
>
>As I understand the spec, these are differential strobes with timing
>referenced to the zero crossing of the true and complement.  This is how
>TriCN implements the DDR 2 strobe in our IP.  Jedec's most recently released
>document muddied the waters a bit when they revised the pindescription to
>say
>
>"... The data strobes DQS, LDQS, UDQS, and RDQS may be used in single
>ended mode or paired with optional complementary signals DQS, LDQS,
>UDQS, and RDQS to
>provide differential pair signaling to the system during both reads and
>writes...."
>
>The spec used to just refer to a "differential strobe" which is certainly
>more clear.
>
>Complementary signaling, at least as I define it, is found in the RLDRAM
>specs which are modeled after QDR SRAM specs.  Here the timing of the DQ is
>measured to the rising edges of the DQS and DQS# ( Or K and K# with SRAMs).
>DQS and DQS# are treated as separate strobes, nominally 180 degrees out of
>phase in complementary signaling.
>
>Hope this helps.
>
>John Ellis
>
>Vice President
>Interconnect Technology
>
>TriCN, Inc.
>
>3605 Vartan Way
>Suite 301
>Harrisburg, PA  17110
>
>Phone:717-657-1002
>Fax:  717-221-1185
>email:jellis@xxxxxxxxx
>
>www.tricn.com
>
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>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Steven M. Waldstein
>Sent: Monday, October 13, 2003 7:35 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] DDR-2 DQS
>
>
>Now that I see that DDR-2 questions are being asked
>I've got mine to ask.
>
>On the current DDR-2 specifications they show
>"differential" DQS as an improvement to improve timing
>accuracy. Can anyone tell me if these are really
>"differential driver and/or receivers" on the memories or
>are these really complimentary strobes?
>
>My reason for asking is that the I often see them referred
>to as differential but the terminations appear to more
>representative of a complimentary implementations.
>
>Also, most of the IP available from vendors to implement
>the controller are complementary implementations. I want to
>make sure these are the proper implementation.
>
>Any personal experience would be helpful. Thanks in advance.
>
>Steve Waldstein
>swldstn@xxxxxxxxxxxx
>
>
>
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