[SI-LIST] DDR2 DIMM question

Hi everybody...

I am novice in the signal integrity and I trying to perform signal integrity
analysis of the DDR2 DIMM module only...
What kind of simulation models I need to simulate electrical loading on the
DDR2DIMM connector?
On the one side is IBIS model of the DRAM, but what is it on the another
side(connector)... 
JEDEC specification is for the Motherboard vendors, Memory modul EBD
Simulation models also...
Who defines level of the signals on the DIMM connector?


Thanks for your help,
Aleksandar Djokic
Bluestar
Serbia

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