[SI-LIST] Re: DDR1 without VTT termination
- From: liuluping 41830 <liuluping@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 02 Apr 2008 16:51:59 +0800
Hi Kathir,
Last week we've talked a similar topic named" DDR2 design issues?" ,Maybe
look more details about this Pull-up terminal resistor Rtt will help you.The
JEDEC's SSTL interface standard is orginaly from the computer industry.At the
PC motherboard ,you will have 2 or more DIMM memory module,of cause it will
have stub .This unbalanced stub will cause reflection and ringing problem at
high speed. The SSTL use two method to solve this SI pr
oblem,one is Stub Seris Resistor(That's why called SSTL),the other is pull up
terminal resistor, Rtt;
The Rtt have two functions:
1.Terminal at the end,eliminate the fist reflection,better for overshoot and
ringing;
2.More fast risf/fall time, good for high speed response.
So it is just for better performance but not neccesary.
If your design not use DIMM module or not have such stub problems,not have
too many DDR loads and the signal speed is not very high,for example
160MHz,you may operate without requiring Rtt---But do enough simulation before
decision.
Good luck!
LIU Luping
Subject: [SI-LIST] Re: DDR1 without VTT termination
Date: Tue, 1 Apr 2008 08:50:27 +0530
From: <ravi.potana@xxxxxxxxx>
Hello Kathir,
Please refer to appnote
http://download.micron.com/pdf/technotes/DDR/tn4614.pdf from Micron.
This may give you some help.
Some system designs can operate without requiring VTT. The approximate
system
boundaries enabling VTT exclusion are:
* Two or fewer DDR components in the system
* Moderate current draw
* Trace length <2in (5cm)
* SI and drive strengths within data sheet limits (determined through
simulation)
Regards
Ravi
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Kathiresan K
Sent: Monday, March 31, 2008 7:48 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR1 without VTT termination
Hi,
I need to have a single chip DDR1 (160 MHz, 16-Bit) memory for a
processor.
I don't want to provide VTT terminations. I'll keep the trace length as
minimum as possible. I may provide series termination but I haven't done
pre-layout simulation yet.
Can somebody please clarify whether it can be designed without VTT
termination? If yes, what can be the maximum trace length I go for? If
I'm providing series termination, should I provide at both the ends for
bi-directional signals?
Regards,
Kathir
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